Efficiently Porting ASIC Flows for FPGA Prototyping

Efficiently Porting ASIC Flows for FPGA Prototyping

Ort: Munich
Unternehmen: Apple Inc.
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Join a rapidly growing team at our Munich design center. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly. The AMS IP team owns a wide portfolio of IPs & complete subsystems going to all the Apple products. In this context the Design Verification Engineer will have to interface with many different teams at Apple and build knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to-end: starting at the specification level, defining the verification strategy & plan, executing the verification, doing performance analysis and handling all the different quality metrics to signoff the verification. This internship would require a good knowledge of RTL design as well as a solid background in object oriented programming. The intern will have to learn & analyse the prototyping flow & methodology used for ASIC design.
She/he will then do a survey on the available techniques to address the different bottlenecks when moving from ASIC to FPGA. The intern will propose Algorithms and proof-of-concept implementation in order to validate the automation techniques. Key case studies will be used to refine the approach and optimize it.
Key Qualifications

• Currently enrolled in a Master’s degree in Computer Science or equivalent
• Knowledge of Object Oriented Programming
• Knowledge of Verilog and/or VHDL (FPGA knowledge is a plus)
• Passionate about micro-electronics
• Scripting language knowledge (perl/python)
• Good written and verbal communication skills
• Experience in working with international teams
• You are available for 6 months or more
  Description
  Learn about FPGA prototyping Define and Design automation techniques for ASIC to FPGA synthesis Perform case study analysis Experiment the new approach on the project execution flow
  Education & Experience
• Bachelor in Computer Science or equivalent
  Additional Requirements
• Bachelor in Computer Science or equivalent
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  Jobs ) Bayern ) München (Kreis) ) IT-Stellen ) Efficiently Porting ASIC Flows for FPGA Prototyping
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