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- Aufgaben: Lead the charge in defining and writing verification plans for cutting-edge tech.
- Arbeitgeber: Join a renowned multinational company at the forefront of digital innovation.
- Mitarbeitervorteile: Enjoy interesting tasks, a dynamic work environment, and opportunities for growth.
- Warum dieser Job: Make an impact in digital IP & SoC verification while collaborating with talented engineers.
- Gewünschte Qualifikationen: M.Sc. in Electrical Engineering or Computer Science with 5+ years in verification required.
- Andere Informationen: Fluency in English and a proactive attitude are essential for success.
Das voraussichtliche Gehalt liegt zwischen 48000 - 84000 € pro Jahr.
Responsibilities:
- Responsible for defining and writing verification plans based on requirements documents.
- Define verification strategy according to design specification documents.
- Responsible for architecting and developing UVM- and software-based verification environments for RTL simulation.
- Define and develop test cases within an appropriate verification framework.
- Create stimulus and assertions, run simulations, and debug test cases on design models (RTL, Gate level, Emulation platform).
- Run regressions, collect, and analyze code/functional coverage.
- Provide guidance and support to verification engineers.
Qualifications:
- Proven experience in testbench design and development using UVM methodology for IP/Subsystem/SoCs.
- Proven experience in verification sign-off at IP/Sub System/SoC level with test plan development, functional & code coverage analysis.
- Proven experience in EDA tools from Cadence (Xcelium, Simvision, Verisium, vManager, Jasper) and/or Synopsys (VCS, Verdi).
- Understanding of software development for embedded CPUs, and experience in developing and debugging software.
- Basic experience in execution of Gate Level Netlist simulation with back-annotated timing; basic experience on writing System Verilog assertions; basic understanding of Formal flow/methodologies.
- Ability to question and identify weaknesses in specifications, tool environments, etc.
- Pro-active attitude with proven experience in digital IP & SoC verification and good communication skills.
- Fluency in English language.
- M.Sc. Degree in Electrical Engineering or Computer Science, with 5+ years of experience on IP/Sub-System/SoC Verification.
Additional Information:
- Interesting tasks in a multinational environment.
- A very renowned company.
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Expert UVM Digital Verification (m/f/d) Arbeitgeber: Hays
Kontaktperson:
Hays HR Team
StudySmarter Bewerbungstipps 🤫
So bekommst du den Job: Expert UVM Digital Verification (m/f/d)
✨Tip Number 1
Make sure to showcase your experience with UVM methodology prominently. Highlight specific projects where you defined verification plans and developed test cases, as this aligns directly with the responsibilities of the role.
✨Tip Number 2
Familiarize yourself with the EDA tools mentioned in the job description, especially those from Cadence and Synopsys. If you have experience with these tools, be ready to discuss how you've used them in past projects during the interview.
✨Tip Number 3
Prepare to demonstrate your problem-solving skills by discussing instances where you identified weaknesses in specifications or tool environments. This will show your proactive attitude and ability to improve processes.
✨Tip Number 4
Since communication skills are emphasized, practice explaining complex technical concepts in simple terms. This will help you convey your expertise effectively during interviews and discussions with the team.
Diese Fähigkeiten machen dich zur top Bewerber*in für die Stelle: Expert UVM Digital Verification (m/f/d)
Tipps für deine Bewerbung 🫡
Understand the Role: Make sure to thoroughly understand the responsibilities and qualifications listed in the job description. Tailor your application to highlight your relevant experience in UVM methodology, testbench design, and verification sign-off.
Highlight Relevant Experience: In your CV and cover letter, emphasize your proven experience with EDA tools from Cadence and Synopsys, as well as your background in software development for embedded CPUs. Use specific examples to demonstrate your skills in digital IP and SoC verification.
Showcase Communication Skills: Since good communication skills are essential for this role, include instances where you successfully collaborated with teams or provided guidance to others. This will help illustrate your ability to work effectively in a multinational environment.
Proofread Your Application: Before submitting your application, carefully proofread your documents to ensure there are no grammatical errors or typos. A polished application reflects your attention to detail, which is crucial in verification roles.
Wie du dich auf ein Vorstellungsgespräch bei Hays vorbereitest
✨Understand the Verification Process
Make sure you have a solid grasp of the verification process, especially UVM methodology. Be prepared to discuss how you've defined and written verification plans in your previous roles.
✨Showcase Your Technical Skills
Highlight your experience with EDA tools like Cadence and Synopsys. Be ready to provide specific examples of how you've used these tools for RTL simulation and verification sign-off.
✨Demonstrate Problem-Solving Abilities
Prepare to discuss instances where you've identified weaknesses in specifications or tool environments. This will showcase your proactive attitude and critical thinking skills.
✨Communicate Effectively
Since good communication skills are essential, practice explaining complex technical concepts in a clear and concise manner. This will help you connect with the interviewers and demonstrate your ability to guide and support other engineers.
