NoC communication profiling for HPC

NoC communication profiling for HPC applications

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Explore high communication HPC application to drive next generation interconnect technology

IMEC’s system technology co-optimization (STCO) program focuses on bringing system level requirements closer to core technologies by tackling scaling, memory, power, and cost implications.

High performance computation (HPC) systems provide resources to solve complex problems which require huge compute capability. Such systems contain hundreds of thousands of CPUs and GPUs all connected to each other to solve different parts of application. Interconnect between such components becomes a bottleneck when an application requires large and/or frequent communication patterns. Optical interconnect between GPUs shows a potential to solve such a problem which can also scale HPC systems. Connectivity of such optical interconnects also require application-level communication patterns for high efficiency.

As part of this work, the candidate will be understanding HPC system infrastructure, whose configuration becomes an important parameter which affect overall performance. Candidate will study different complex applications and model them for simulation tools and evaluate different applications.

Required background: Computer science, parallel computing on cluster, GPU/CPU system level architecture, programming (C++/Python/CUDA)

Type of project : Combination of internship and thesis

Duration : 6-9 months

Required degree : Master of Science, Master of Engineering Technology, Master of Engineering Science

Required background : Computer Science, Electrotechnics/Electrical Engineering

Supervising scientist(s) : For further information or for application, please contact: Aakash Patel (Aakash.Patel@imec.be) and Dwaipayan Biswas (Dwaipayan.Biswas@imec.be)