Internship: RTL to Silicon - Comprehensive Power Analysis and Optimization in VLSI Design (f/m/div)

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Job Description

• Expand your horizons: You work with RTL-level (Register-Transfer Level) designs and optimize them for power exploration
• Reliable work: You are responsible for simulations to integrate dynamic and switching activity
• Take responsibility: You perform synthesis and analyze power at gate level
• Precise work: You work on physical design steps to measure post-layout power
• Focus on the future: You apply and evaluate power optimization techniques at different abstraction levels
• Data is everything: You document findings and contribute to internal reports and publication

Your Profile

• Study field: You are currently completing a Master´s degree in Electrical and Computer Engineering or a similar discipline
• Know-How: You have a strong background in digital design and RTL (Verilog/SystemVerilog) and a good understanding of power concepts and switching activity
• Experience: You have gained first experience with simulation tools (Xcelium, ModelSim, VCS, etc.)
• Skills: You are familiar with EDA tools for synthesis (e.g., Design Compiler, Genus) and power analysis tools (e.g., Joules) and have a good knowledge of verification methodologies
• Language skills: You have fluent English skills, both written and spoken; German is a plus

Please attach the following documents to your application:

• CV in English
• Certificate of enrollment at university
• Excerpt of the study regulations for the mandatory internship (if applicable)
• Latest grades transcript (not older than 6 months)
• High school report

Contact:
Julia Flammersberger

Further links:
Find out what we are looking for in your CV
Find out how the student application process works with us
Discover our student website

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