Senior OSAT Engineer

Job Details

Job Description

About Altera

Altera is a global leader in FPGA and programmable logic solutions, enabling innovation in data center, communications, automotive, aerospace, and industrial markets.

As we expand manufacturing capabilities for next-generation programmable devices, we are strengthening our OSAT engineering organization to deliver world-class backend manufacturing performance.

Role Summary

We are seeking a highly skilled

Senior OSAT Engineer to drive outsourced assembly and test engineering activities across Altera’s global supplier network.

You will lead NPI readiness, yield optimization, cost improvements, and qualification activity for packaging and test flows supporting Altera’s FPGA/So C product lineup.

This role requires strong semiconductor backend engineering experience, hands‑on problem solving, and the ability to collaborate closely with OSAT partners and cross‑functional stakeholders.

Key Responsibilities

• Lead technical engagement with OSAT suppliers on assembly and test process development, yield ramp, quality improvement, and volume manufacturing readiness.
• Drive new product introduction (NPI) from engineering builds through production release, ensuring OSAT capability meet electrical/thermal/mechanical requirements for FPGA and So C products.
• Optimize packaging and test architectures for performance, cost, and reliability: advance packaging, flip‑chip BGA, high‑pin‑count packages, substrate technologies, wafer‑level solutions, burn‑in/FT coverage.
• Monitor and improve manufacturing performance using data‑driven analysis; identify systemic issues and lead root cause / corrective actions.
• Partner with Test Engineering, Package Design, Product Engineering, DFM, and Quality teams on process optimization, failure analysis, and manufacturability improvements.
• Implement and maintain process control systems, SPC methodologies, automation improvements, and lean manufacturing principles at OSAT.
• Support cost reduction initiatives including BOM optimization, process simplification, and cycle time improvements.
• Track supplier performance metrics (yield, DPPM, cost, cycle time, OEE) and provide updates with risk assessments and mitigation plans.
• Lead or support reliability testing and package qualification activities aligned to industry standards (JEDEC, IPC, AEC‑Q).
• Maintain strong technical relationship and communication cadence with OSAT partners to ensure transparency, collaboration, and escalation management.

Qualifications

• Bachelor’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.
• 10+ years of semiconductor assembly, packaging, or test engineering experience.
• Hands‑on experience with OSAT manufacturing environments, including wafer finishing, substrate attach, interconnect packaging, test, and burn‑in.
• Strong technical understanding of backend manufacturing flows: flip‑chip, wire bond, underfill, molding, final test, reliability stress and analysis.
• Proven ability to analyze yield, reliability, and cost data to drive engineering decisions and improvements.
• Demonstrated success working with international suppliers and cross‑functional teams.
• Strong statistical analysis, written and verbal communication skills, including technical reporting and supplier engagement.
• Preferred Qualifications
• FPGA, ASIC, or So C backend experience, particularly high‑pin‑count or high‑power devices.
• Experience in automotive or high‑reliability product qualifications (AEC‑Q / ISO standards).
• Familiarity with advanced packaging: 2.5D/3D, fan‑out WLP, heterogeneous integration.
• Knowledge of supply chain risk mitigation, dual sourcing, and volume scaling strategies.
• Experience with automation, traceability systems, and smart factory/manufacturing analytics.
• Job Type
• Regular
• Shift
• Shift 1 (Taiwan)
• Primary Location
• Virtual Taiwan
• Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

#J-18808-Ljbffr