Experienced Cellular IP Design Engineer (m/f/d) In this role, you will be a key part of the Cellular SoC IP team in Munich or Linz. As an IP Design engineer, you are responsible for developing highly customized hardware IPs for digital signal processing and integrating IPs into SoCs. You will work closely with SoC architects, System engineers, Design verification, Silicon validation teams, STA/DFT/Power specialists, and Physical designers to develop IPs & SoCs that meet Apple devices’ power, performance, and area goals.
Description As a Cellular design engineer, you will be developing, integrating & verifying IP sub-components for a cellular transceiver System on a Chip. You would be responsible for defining and driving the implementation, timing closure, and power optimizations in close collaboration with a multi-disciplinary group from system, digital, analog & firmware design, to design verification, and physical design teams, which will support your daily work. Your work will not be limited to design. It will cover end-to-end responsibility across the project lifecycle for the IPs developed from concept to design, verification, integration, silicon validation, and finally, in-field operation.
Minimum Qualifications
Experienced with crafting low-power customized hardware for digital signal processing. Understanding of signal processing principles. Abstract modeling skills for synthesis and simulation using modern modeling language. (Verilog / System Verilog).
Advanced hands‑on experience in multiple sophisticated ASIC or FPGA designs, spanning from concept to productization.
Good hands‑on experience with digital logic design and quality checks, such as Lint and CDC/RDC.
Proficient in using (System)Verilog, the ability to analyze RTL/Netlist designs, and outstanding debugging skills to solve technical challenges.
Familiar with day‑to‑day usage of scripting languages (e.g., TCL, Python, Perl, shell), Linux, and revision control systems (e.g., Perforce), database management, and releases.
Passion for owning/driving design topics using well‑defined metrics, a strong initiative, and ownership of responsibilities, productive, and able to meet daring deadlines.
Advanced interpersonal skills and the ability to communicate abstract concepts to different stakeholders. Excellent problem‑solving skills and the ability to find effective technical solutions between partners in RTL design, Firmware, System Engineering, Power, and Physical Design teams.
English language proficiency is a requirement for this position.
Preferred Qualifications
Experience with on‑chip communication buses & fabrics like AMBA/Wishbone and processor sub‑systems would be a plus.
Experience with SystemC/C++ hardware design modeling, high‑level synthesis, and logical synthesis would be desirable.
Experience applying Machine Learning or AI techniques to optimize digital hardware design processes and workflows (e.g., RTL generation, power/timing optimization, design space exploration, or design flow automation).
A bachelor's or master’s, or Ph.D. in electrical engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent, paired with extensive years of industry work experience.
The minimum salary pursuant to the applicable collective bargaining agreement amounts to €81,580 gross per year for full‑time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.
Apple is an equal‑opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities.
At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits, and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
At Apple, base pay is one part of our total compensation package and is determined within a range. This range provides the opportunity to progress as you grow and develop within a role. The base pay for this role is between €95,000 and €187,900 and reflects a full‑time equivalent. Your base pay will depend on contractual hours, skills, qualifications, experience, location, and any relevant collective bargaining agreement provisions.
Apple employees are eligible to participate in the Apple Inc. discretionary stock programs. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. You’ll also receive benefits including: Comprehensive insurance benefits, retirement benefits, a range of discounted products and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Learn more about Apple Benefits
Note: Apple benefit, compensation and discretionary stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Learn about accessibility in Apple’s workplace
#J-18808-Ljbffr
Description As a Cellular design engineer, you will be developing, integrating & verifying IP sub-components for a cellular transceiver System on a Chip. You would be responsible for defining and driving the implementation, timing closure, and power optimizations in close collaboration with a multi-disciplinary group from system, digital, analog & firmware design, to design verification, and physical design teams, which will support your daily work. Your work will not be limited to design. It will cover end-to-end responsibility across the project lifecycle for the IPs developed from concept to design, verification, integration, silicon validation, and finally, in-field operation.
Minimum Qualifications
Experienced with crafting low-power customized hardware for digital signal processing. Understanding of signal processing principles. Abstract modeling skills for synthesis and simulation using modern modeling language. (Verilog / System Verilog).
Advanced hands‑on experience in multiple sophisticated ASIC or FPGA designs, spanning from concept to productization.
Good hands‑on experience with digital logic design and quality checks, such as Lint and CDC/RDC.
Proficient in using (System)Verilog, the ability to analyze RTL/Netlist designs, and outstanding debugging skills to solve technical challenges.
Familiar with day‑to‑day usage of scripting languages (e.g., TCL, Python, Perl, shell), Linux, and revision control systems (e.g., Perforce), database management, and releases.
Passion for owning/driving design topics using well‑defined metrics, a strong initiative, and ownership of responsibilities, productive, and able to meet daring deadlines.
Advanced interpersonal skills and the ability to communicate abstract concepts to different stakeholders. Excellent problem‑solving skills and the ability to find effective technical solutions between partners in RTL design, Firmware, System Engineering, Power, and Physical Design teams.
English language proficiency is a requirement for this position.
Preferred Qualifications
Experience with on‑chip communication buses & fabrics like AMBA/Wishbone and processor sub‑systems would be a plus.
Experience with SystemC/C++ hardware design modeling, high‑level synthesis, and logical synthesis would be desirable.
Experience applying Machine Learning or AI techniques to optimize digital hardware design processes and workflows (e.g., RTL generation, power/timing optimization, design space exploration, or design flow automation).
A bachelor's or master’s, or Ph.D. in electrical engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent, paired with extensive years of industry work experience.
The minimum salary pursuant to the applicable collective bargaining agreement amounts to €81,580 gross per year for full‑time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.
Apple is an equal‑opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities.
At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits, and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
At Apple, base pay is one part of our total compensation package and is determined within a range. This range provides the opportunity to progress as you grow and develop within a role. The base pay for this role is between €95,000 and €187,900 and reflects a full‑time equivalent. Your base pay will depend on contractual hours, skills, qualifications, experience, location, and any relevant collective bargaining agreement provisions.
Apple employees are eligible to participate in the Apple Inc. discretionary stock programs. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. You’ll also receive benefits including: Comprehensive insurance benefits, retirement benefits, a range of discounted products and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Learn more about Apple Benefits
Note: Apple benefit, compensation and discretionary stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Learn about accessibility in Apple’s workplace
#J-18808-Ljbffr
Experienced Cellular IP Design Engineer (m/f/d) Arbeitgeber: Apple Inc.
Apple ist ein hervorragender Arbeitgeber, der nicht nur innovative Produkte schafft, sondern auch eine inklusive und vielfältige Arbeitskultur fördert. In Mainz haben Mitarbeiter die Möglichkeit, in einem dynamischen Umfeld zu arbeiten, das kontinuierliches Lernen und persönliche Entwicklung unterstützt. Mit einem starken Fokus auf Teamarbeit und Kundenservice bietet Apple seinen Mitarbeitern die Chance, ihre Leidenschaft für Technologie auszuleben und gleichzeitig einen positiven Einfluss auf die Gemeinschaft zu haben.
