Analog Layout Automation Engineer (f/m/d)

Summary

Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems‑on‑chip (SOCs)!

Our SOCs, featuring multi‑billion transistors, are the heart of iconic devices like i Phones, i Pads, and Macs.

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed‑Signal (AMS) circuits, covering Ser Des, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency.

Description

As an Analog Layout Automation Engineer, you’ll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI‑powered, CAD tools to create high-performance analog and mixed‑signal layouts.

You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next‑generation SOCs.

You’ll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data‑driven design insights.

• Minimum Qualifications
• BS and extensive years relevant industry experience.
• Preferred Qualifications
• Experience designing analog and mixed‑signal layouts in deep‑submicron CMOS and Fin FET technologies.
• Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis.
• Solid understanding of supervised and self‑supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization.
• Hands‑on experience with Py Torch for model development and experimentation.
• Demonstrated ability to automate layout tasks, flows, and quality checks using scripting and CAD tools.
• Proven record in implementing high‑quality analog layouts with tight device matching, low noise, and low power consumption.
• Familiarity with failure‑prone circuit/layout structures, analog and DFM best practices, and the ability to diagnose and resolve layout‑related issues.
• Strong proficiency in custom and standard‑cell floor planning, hierarchical layout assembly, and physical integration.
• Understanding of image processing fundamentals, spatial representations, multi‑channel image handling, segmentation, and object detection concepts.
• Technical understanding of IR drop, RC delay, electromigration, self‑heating, coupling capacitance, and related reliability concerns.
• High proficiency in interpreting physical verification reports, including DRC, ERC, and LVS.
• Experience using advanced Cadence Virtuoso features (XL, EAD, APR, Constraint Manager), and familiarity with Cadence Innovus.
• Experience with CAD automation workflows and PCell creation.
• Excellent communication skills and the ability to work effectively with cross‑functional teams.
• Apple is an Equal Opportunity Employer that is committed to inclusion and diversity.

We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

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We will work with applicants to make any reasonable accommodations.

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