Senior Hardware Compute Architect (f/m/d)

About us

We see the semiconductor industry as a realm of possibility.

We see opportunity.

We see the profound impact that our graphene solutions will have in transforming the industry.

We invite you to join us in driving change with our fundamentally human‑centered approach, uniting bright minds around a shared vision.

The vision is: Prove to everybody that you can make a fundamental change.

Prove with your knowledge and skills how things can be done differently.

• Together, we can change the paradigm of how the world connects
• About our technology

The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology.

We connect chips to high‑throughput, low‑delay computing networks.

The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one.

Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude

In short, we connect chips to create powerful and energy‑efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution

The Role

We are seeking a skilled Senior Hardware Compute Architect at Black Semiconductor to own the hardware architecture of our next‑generation hybrid compute engine, combining electronic compute capabilities with photonic compute technologies.

You will define the compute architecture, memory hierarchy, data fabric, and system interfaces that enable dynamic workload execution across electronic and photonic domains.

Working closely with the Architecture Lead, Senior Software Compute Architect, photonics teams, and downstream implementation teams, you will drive system‑level architectural decisions by evaluating performance, power, area, and manufacturability trade‑offs.

Your work will translate workload requirements into an implementable hardware architecture for a new class of compute systems.

This role bridges compute architecture, heterogeneous system design, and electronic‑photonic co‑design.

• To join our team, you should be excited to
• Define the hardware architecture of a hybrid compute engine, including execution units (scalar, vector, tensor/matrix), memory hierarchy, memory tiering strategies, and the interfaces required to enable cooperation between electronic and photonic compute domains.
• Architect the system data fabric and interconnect infrastructure, including bandwidth, latency, coherency, and die‑to‑die communication requirements using technologies such as UCIe‑class links, CXL, UALink, and NVLink‑class fabrics.
• Partner with the Software Compute Architect to define hardware/software interfaces and workload mapping strategies, determining when operations should execute through electronic versus photonic compute paths.
• Evaluate architectural options through quantitative modeling, analyzing performance, power, area, and scalability trade‑offs to guide system‑level decisions before silicon implementation.
• Collaborate with photonics architecture, circuit design, RTL, physical design, and packaging teams to translate compute primitives into implementable system‑level architectures.
• Own the hardware architecture specification through sign‑off, ensuring alignment between system requirements and downstream implementation teams.
• Your Qualifications
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
• 5+ years of experience designing compute hardware architecture at the So C or system level, ideally involving heterogeneous computing, accelerators, or specialized compute architectures.
• Deep expertise in compute architecture, including execution units (scalar, vector, tensor/matrix), workload mapping, memory hierarchy, and system‑level architecture trade‑offs.
• Strong experience architecting high‑performance interconnects, data fabrics, and heterogeneous compute systems, including technologies such as UCIe, CXL, UALink, NVLink‑class, or comparable architectures.
• Experience with architectural modeling and quantitative analysis of performance, power, area, and system scalability to guide hardware architecture decisions.
• Proven ability to collaborate across hardware and software teams to define interfaces, requirements, and system‑level design decisions.
• Experience with architecture modeling and simulation tools, interconnect protocols, and system design workflows, including performance/power modeling environments, CXL, UALink, NVLink‑class fabrics, UCIe, Python, C++, System C, and architecture specification tools used to develop implementable designs for RTL, physical design, and packaging teams.
• Familiarity with photonic or optical compute concepts and their integration with electronic compute architectures will be considered a plus.
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