Lead Application Engineer

Cadence is a pivotal leader in electronic design, with more than 30 years of computational software expertise. Our Intelligent System Design strategy delivers software, hardware, and IP that turn design concepts into reality for innovative companies worldwide.

Job Title: Lead Application Engineer

Location: Feldkirchen (Munich), Germany

Reports to: Application Engineering Group Director

Job Overview

As a Lead Application Engineer, you will serve as a trusted technical advisor to leading semiconductor companies, driving the adoption of Cadence’s Digital Implementation and Signoff solutions to help customers achieve industry-leading Power, Performance, and Area (PPA) results. You will shape how next‑generation silicon is brought to market, leveraging AI‑driven design technologies to accelerate design closure and solve complex implementation and signoff challenges, while working with Cadence R&D to influence product direction.

Job Responsibilities

• Lead customer evaluations, benchmarks, and proof‑of‑concept projects, guiding customers through complex technical decisions to accelerate design closure.
• Provide deep technical expertise in Power Analysis, Electromigration/IR (EM/IR) Signoff, and advanced‑node implementation methodologies.
• Develop and deliver tailored customer presentations, technical workshops, and training sessions that build capability and confidence in Cadence’s Digital Full Flow.
• Collaborate with sales teams to identify and qualify new business opportunities, translating technical insights into clear value propositions.
• Mentor and develop junior Application Engineers, contributing to knowledge‑sharing practices and raising the technical bar across the AE organisation.
• Partner with R&D and Product Engineering to diagnose and resolve complex customer challenges and actively influence the product roadmap.
• Evaluate and communicate the impact of AI‑assisted design methodologies to customers, positioning Cadence’s AI‑enabled and agentic design solutions as strategic differentiators.
• Maintain up‑to‑date expertise in advanced nanometer implementation techniques and low‑power design standards (UPF/CPF).

Job Qualifications

• Degree in Electrical, Electronic Engineering, Microelectronics, or a related discipline, or equivalent industry experience.
• 5–8 years of experience in Physical Design, Digital Implementation, Signoff, or related semiconductor design disciplines.
• Hands‑on experience with Power Analysis and EM/IR Signoff (required).
• Strong customer‑facing communication skills and a structured approach to technical problem‑solving.
• Fluent English communication skills, both written and spoken.

Skills & Preferences

• Experience with Cadence Digital Full Flow tools including Innovus, Tempus, Voltus, and Joules.
• Advanced nanometer implementation experience.
• Familiarity with low‑power design techniques and standards (IEEE 1801, UPF, CPF).
• Experience in customer‑facing technical roles.
• Exposure to AI‑assisted design methodologies.

Additional Information

• Join a highly experienced and collaborative team of Application Engineers supporting leading semiconductor companies across Europe.
• Play a key role in driving adoption of next‑generation AI‑enabled and agentic design solutions for some of the industry’s most advanced semiconductor customers.
• Key stakeholders include customers’ design and engineering leads, Cadence R&D teams, and the European sales organisation.
• Primary tools include Cadence’s Digital Full Flow suite: Innovus, Tempus, Voltus, Joules, and related implementation and signoff platforms.

Travel: Approximately 10% of travel is expected, primarily to support customer engagements and technical workshops across Europe.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.