Ellisys in Geneva, Switzerland, seeks a highly analytical engineer with a strong programming background in VHDL or Verilog to join our protocol analysis team. You will design software components for protocol analyzers and testers, and handle large data sets with efficient processing.Candidates should have high-speed logic design experience, familiarity with Xilinx toolchains, and knowledge of USB, Bluetooth or Wi‑Fi protocols. #J-18808-Ljbffr
FPGA Design Engineer (VHDL/Verilog) - High-Speed Protocols in Geneva
FPGA Design Engineer (VHDL/Verilog) - High-Speed Protocols in Geneva
Geneva Vollzeit Vor Ort
