Senior Scientist for Digital Design with focus on RISC-V (f/m/d)

Computer science » Programming

Computer science » Other

Engineering » Other

Organisation/Company: Silicon Austria Labs (SAL)

Research Field: Computer science » Computer architecture, Computer science » Programming, Computer science » Other, Engineering » Computer engineering, Engineering » Other

Researcher Profile: First Stage Researcher (R1)

Country: Austria

Application Deadline: 14 Jun 2025 – 21:59 (UTC)

Type of Contract: Permanent

Job Status: Full-time

Is the job funded through the EU Research Framework Programme? Not funded by a EU programme

Is the Job related to staff position within a Research Infrastructure? No

Offer Description

YOUR FUTURE RESPONSIBILITIES

Are you passionate about shaping the future of embedded computing architectures? Do you have the expertise and ambition to drive innovation in digital IC design? Join us as a Senior Scientist for Digital Design with a Focus on RISC-V and lead the way in developing cutting-edge, sustainable, and intelligent computing solutions.

Key Responsibilities:

• Develop future sustainable, dependable, and intelligent embedded computing architectures.
• Drive research in VLSI/digital design with a focus on RISC-V and related processor architectures and accelerators.
• Contribute to the development of accurate design specifications for digital control blocks.
• Deliver complex digital IP to meet schedule, area, power, and performance targets.
• Work with digital verification teams to create verification plans.
• Collaborate with laboratory teams to create and verify FPGA-based prototypes.
• Collaborate with industry and academia partners.
• Lead research projects and participate in the acquisition of industry projects and funding grants.
• Publish your work in leading journals and present at conferences.

YOUR PROFILE

Educational Background:

• PhD in digital IC design with at least 3 years of relevant experience, or
• MSc in a relevant field with at least 5 years of relevant experience.

Technical Expertise:

• Demonstrate strong proficiency in HDLs (SystemVerilog, VHDL ).
• Excel in architecture exploration and micro-architecture development .
• Possess in-depth knowledge of on-chip infrastructure (AMBA/PCIe/USB/JTAG, NoC).
• Have a solid background in silicon development and digital IP design/integration .
• Utilize experience with back-end tools (synthesis and Place & Route).
• Exhibit proficiency in Static Timing Analysis tools and Clock Domain Crossing .
• Show expertise in functional and formal verification .
• Apply skills in scripting languages (Tcl, Python, Perl, MATLAB, Shell-scripting).
• Leverage experience with EDA tools (simulator/debug/synthesis/timing analysis/place & route) from major vendors (Synopsys, Cadence, Mentor).
• Experience with FPGA tools (e.g., Xilinx).
• Communicate effectively in verbal and written English ; knowledge of German is an advantage.

Additional Skills:

• Proven project management experience.
• Autonomous, well-organized, and thrive in a dynamic and multicultural team environment.
• Experience in team leadership or PhD supervision is highly desirable.
• Effective in strategy development is an advantage.
• Strong track record in business development and winning projects.

If you are ready to take your career to the next level and make a lasting impact on the future of digital design, we want to hear from you. Apply today and become a key player in our innovative team!

IMPORTANT FACTS ABOUT SAL

• Diverse research activities with many technical challenges.
• State-of-the-art laboratory facilities and equipment.
• Location in the heart of Europe in Austria – relocation support for non-European nationalities.
• Internal and external training opportunities for career development.
• Home office in Austria (max. 40%) and work from anywhere in the European Union possible (<25%).
• Family & children friendly – actively shaping the compatibility of family and career.
• “Vital4SAL” to promote a healthy workplace (e.g. SAL coaching pool, trainings on mental health, physical activities, healthy snacks, 24/7 accident insurance).
• € 4 per day meal allowance in restaurants or € 2 per working day in supermarkets.
• Public transport initiative (subsidy for the “Klimaticket”).
• Start: as soon as possible.

This position is subject to the Collective Agreement for employees in non-university research (Research CA) starting in occupational group F (F1 salary = EUR 4.594,- paid 14 times a year, based on 38.5 hours per week). For this position, we offer competitive salaries and additional benefits based on your experience and qualifications, starting with a minimum gross salary of EUR 70.000 (annual, based on an All-in contract and bonus).

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