Senior Digital Design Engineer in München

Senior Digital Design Engineer – RTL / Verilog / System Verilog / Digital Signal Processing

We are currently partnered with a semiconductor technology organisation specialising in advanced MEMS-based precision timing solutions.

This opportunity focuses on the design and implementation of digital logic for complex mixed-signal timing products, covering micro-architecture development, RTL design, synthesis and timing analysis.

The role involves working closely with cross-functional engineering teams throughout design, validation and silicon bring-up.

Key responsibilities

• Develop micro-architecture specifications for logic circuits based on product requirement documentation.
• Translate micro-architecture specifications into RTL designs using Verilog or System Verilog.
• Develop standalone testbenches to verify RTL behaviour.
• Write and verify System Verilog Assertions (SVA).
• Define timing constraints and clock configurations for synthesis and place-and-route tools.
• Run industry-standard synthesis tools, such as Cadence Genus or Synopsys Design Compiler, and resolve timing issues.
• Evaluate design trade-offs across timing, area and power, identifying opportunities for optimisation.
• Analyse Static Timing Analysis (STA) reports using industry-standard tools such as Prime Time.
• Collaborate with analog, verification, backend, system and test engineering teams.
• Support post-silicon bring-up, validation and debugging.
• Key requirements
• Master's degree in Electrical Engineering, plus 5 years of relevant industry experience.
• Excellent written and verbal communication skills in English.
• Proficiency in Verilog and System Verilog.
• Strong understanding of digital logic design fundamentals, including clock dividers, multi-clock designs, clock-domain crossing (CDC), FIFOs and finite-state machines (FSMs).
• Basic understanding of discrete-time signal processing, including FIR and IIR filter design.
• Solid experience across the digital design flow, including RTL design, synthesis, timing constraints and static timing analysis.
• Proficiency in scripting languages such as Perl, Tcl or Python.
• Keywords

Senior Logic Design Engineer / Digital Logic Design / RTL Design / Verilog / System Verilog / System Verilog Assertions / SVA / Micro-architecture / Mixed-Signal Digital Design / Digital IC Design / Clock Divider / Multi-Clock Design / Clock-Domain Crossing / CDC / FIFO / FSM / Finite-State Machine / Digital Signal Processing / DSP / FIR Filters / IIR Filters / Digital Phase-Locked Loop / DPLL / Digital Arithmetic / RTL Verification / Testbench Development / Logic Synthesis / Cadence Genus / Synopsys Design Compiler / Timing Constraints / Static Timing Analysis / STA / Prime Time / Timing Optimisation / Power Optimisation / Low-Power Design / Perl / Tcl / Python / MATLAB / Simulink / Silicon Bring-Up / Post-Silicon Validation / Debugging

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