Senior PLL Design Engineer

Senior AMS (PLL) Design Engineer About the Role We\’re seeking a Senior PLL Design Engineer to join our analog/mixed-signal design team. You’ll design, simulate, and verify high-performance PLLs for SoC and mixed-signal applications, working with cross-functional teams to deliver silicon-proven solutions on advanced nodes like 22FDX and FinFET/FD-SOI. Key Responsibilities Design PLL components (VCOs, phase detectors, charge pumps, loop filters, dividers) Perform schematic, behavioral, and transistor-level simulations (Spectre, HSPICE, Verilog-A/AMS) Optimize for jitter, power, and area Work with layout engineers to ensure design integrity Support silicon validation, debugging, and SoC integration Contribute to design reviews and documentation Your Profile M.Sc. or Ph.D. in Electrical Engineering or similar Proven experience in analog/mixed-signal IC design (PLLs, SerDes, DDR) Strong knowledge of PLL theory, jitter/noise modeling, and analog blocks (op-amps, VCOs, DLLs) Skilled in Cadence tools, Spectre, Verilog-A/SystemVerilog-AMS Familiar with full-custom layout and verification Experience with advanced CMOS nodes Strong team player with good communication skills If this is of interest then please get in touch and we can discuss: lg@eu-recruit.com By applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)