Wafer-Scale Networks Intern: NoC & LLM Parallelism

Huawei Research Center Zürich is seeking a researcher with expertise in communication and computation for wafer-scale systems. The candidate will conduct advanced research on Network-on-Chip design, focusing on efficient interconnects and workload optimization. The ideal applicant holds a Master’s in Electrical Engineering or a related field, with strong skills in network architecture and problem-solving. Enjoy the benefits of a dynamic team and a high-quality life in Zurich.
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