pb**All applicants must have the right to work in Switzerland** /b /ppOur client is building a world-class silicon team and is looking for a Lead Physical Design Engineer to take ownership of the complete RTL-to-GDSII implementation flow for complex IP and SoC subsystems. This is a hands‑on leadership role where you’ll not only define methodologies and drive execution but also help scale a new backend team around you. /ppIn this position, you’ll define best practices, own PPA and sign‑off quality, and act as the bridge between digital design, custom design, and verification teams. The role combines deep technical involvement with the opportunity to shape the physical design strategy from the ground up. /ph3Key Responsibilities /h3ullibEnd-to-end ownership: /b Oversee the entire RTL-to-GDSII flow — from synthesis and floorplanning through place route, CTS, STA, and sign‑off. /lilibMethodology flow: /b Define, maintain, and automate a robust implementation flow including constraints, UPF/CPF, and sign‑off checks. /lilibPPA closure: /b Drive timing and power closure across multiple corners and modes; lead ECO cycles and ensure strong correlation between synthesis, PR, and sign‑off. /lilibIntegration: /b Handle integration of custom macros, SRAMs, and I/O, including clocking strategy, CDC, and hierarchical designs. /lilibLow‑power design: /b Own power intent definition and implementation, including isolation, retention, and level‑shifting strategies. /lilibTeam leadership: /b Build and mentor a backend team (5+ engineers), define ownership areas, and establish repeatable, high‑quality sign‑off standards. /lilibAutomation: /b Develop reproducible, automated flows using Tcl/Python, CI/CD pipelines, and metrics dashboards for continuous improvement. /lilibFoundry interface: /b Collaborate closely with foundry partners on PDK updates, reliability rules, and design sign‑off requirements. /li /ulh3Skills Experience /h3ulli5+ full tapeouts owning blocks or subsystems through to sign-off. /liliDeep expertise in one major EDA tool chain (Synopsys or Cadence). /liliProven experience in timing closure, MCMM STA, and hierarchical design integration. /liliStrong knowledge of UPF/CPF for multi‑voltage and power‑gated designs. /liliHands‑on experience with grid planning, IR/EM analysis, power optimisation, and ECO implementation. /liliConfident in taking technical ownership and guiding others towards sign‑off-quality results. /li /ulpTel - /ppLinkedIn - /p #J-18808-Ljbffr
Lead Physical Design Engineer Arbeitgeber: IC Resources
Unser Unternehmen ist ein hervorragender Arbeitgeber, der Ihnen die Möglichkeit bietet, in einem dynamischen und technisch anspruchsvollen Umfeld zu arbeiten. Hier können Sie Ihre Fähigkeiten als ASIC Project Manager voll entfalten, während Sie eng mit talentierten Ingenieurteams zusammenarbeiten und an innovativen Projekten mitwirken. Wir fördern eine offene und kollaborative Unternehmenskultur, die auf kontinuierliches Lernen und persönliche Entwicklung abzielt, und bieten Ihnen die Chance, aktiv zur Gestaltung unserer wachsenden Organisation beizutragen.
