Lead Custom Design Engineer in Zürich

Zürich, SwitzerlandSeniority: 7+ years (custom digital, analog, or memory), team leadershipLead the development of high-performance, custom based digital compute or SRAM memory designs to power our compute-in-memory SRAM (ComputeRAM®). You will own architecture, circuit design, verification, and silicon correlation for advanced nodes down to 5 nm and below, and you will lead a small team of custom designers and layout engineers to predictable, production-grade outcomes. Expect hands-on work on bitcell-adjacent periphery, datapath interfaces, optimizing data movement, as well as tight collaboration with full-custom layout, digital, backend, DFT, and test.What you’ll doOwn the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and CxR-adjacent custom blocks.Design & verify memory or datapath subsystems, including sense amps, data drivers, multipliers, adders, register files, timing/control FSMs, etc..Engineer for advanced nodes: close on variation (corners, Monte-Carlo), stability, noise/IR drop, device reliability, and wake-up/low-power behaviors in FinFET and FDSOI.Integrate for product: define clean digital boundaries (standard-cell and bus interfaces), latency/handshake contracts, and timing budgets so blocks drop into a digital-on-top mixed-signal flow.Silicon correlation: plan bring-up, build characterization benches, analyze ATE data, and publish correlation and errata with clear fixes.Redundancy & test: specify and validate redundancy/repair schemes; work with DFT (MBIST and Scan) test coverage; sign off on a production test plan.Partner with layout: co-plan floorplans, matching/guarding, shielding, and routing topologies; review extraction and fix EM/IR issues early.Elevate method & team: coach designers, run reviews, enforce checklists, and grow automation (Python/Tcl) for regressions, reporting, and collateral generation.Outcomes (first 18 months)Tape-in and silicon of at least one production-grade CxR custom memory block meeting spec across PVT, with signed correlation and test reports.A reusable design kit (models, constraints, verification plans, char scripts, checklists) that shortens the following variant’s cycle time.A high-functioning custom team with clear ownership (periphery, timing/control, modeling, characterization) and reliable delivery metrics.Quantified PPA and yield gains from design or methodology improvements you led.RequirementsMS or PhD in Electrical/Computer Engineering (or similar) and 7+ years in custom digital, memory, or analog design.Track record of end-to-end ownership of production-grade functional blocks, including sign-off and silicon correlation.Deep understanding of high-performance and low-power circuit design on FinFET nodes (stability, variation, leakage, performance).Experience leading a small team (mentoring, reviews, planning) and coordinating tightly with layout, digital, backend, DFT, and test.Clear communication, structured documentation, and a quality-first mindset.Nice to haveScripting for design and characterization automation (Python, Tcl) and model/report generation.Experience with memory compilers, characterization flows, and verification Website exposure to align device, bitcell, and periphery choices with product goals.Background with production test strategies.Familiarity with compute-in-memory constraints and with integrating custom memory into large digital systems.Interview flow (indicative)30-min intro with HR (role/context)First Technical deep diveSecond Technical Deep Dive(Optional) Third Technical Deep DiveSystems/product conversation with management #J-18808-Ljbffr