Senior Verification Lead: Mixed-Signal, SystemVerilog/UVM

Infineon Technologies AG is seeking a Senior Staff Engineer Verification in Villach, Austria. In this role, you will define and execute comprehensive verification strategies for Mixed-Signal designs and lead efforts to ensure project excellence. The ideal candidate has over 6 years of experience in Digital Verification, with expertise in tools like SystemVerilog and UVM. We offer competitive compensation according to industry standards, alongside opportunities for professional growth.
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