Staff Engineer -Pre Silicon Validation (Emulation)Engineer

The ICW-SoC Team is searching for a hands-on, team-oriented Emulation Engineer. In this role, the engineer will be responsible for prototyping the SoCs on FPGA, any knowledge of HAPS and emulation platforms like ZeBu/Palladium is a plus. We are looking for a self-motivated and experienced engineer who can work with minimal supervision in our SoC team and be able to work closely with our global design teams.

Job Description
Responsibilities:

• Responsible for prototyping SoC designs on

-FPGA based platforms like Synopsys HAPS, Seimens Pro FPGA, S2C FPGA platform.
-Emulators like Synopsys ZeBu, Cadence Palladium.

• Overseeing new board level HW development to enable Pre-Silicon validation on FPGA platforms.
• Identify the need for models for Analog blocks and Hard IPs, develop/coordinate with IP teams to get emulation/FPGA models for prototyping.
• RTL Clock tree optimization/Simplification to make it FPGA friendly. Timing analysis and Timing constraints generation for FPGAs.
• Pro-actively work with different teams like RTL teams and DV teams to get inputs on design features and to test/validate/debug the design on the emulator/FPGA platforms.
• Supporting all stakeholders globally for the FPGA platforms and Emulators.
• Work with 3rd party vendors to get support for emulators, FPGA tool chain, other IP vendors to debug issues during prototyping and testing.
• Development of testbenches to validate various IO protocols/interfaces based on the SoC being prototyped.
• Help, drive improvements on-the-fly (as project executes).
• Ensure an inclusive teamwork environment, inspire team members, and role model.

Your Profile
Required Skills:

• B.Tech with 6+ years of experience or M Tech with 5+ year of experience in ASIC prototyping
• Hands on experience in FPGA flow and tools.
• Hands on experience in Synopsys HAPS Flow and related tool chain is a plus
• Hands on experience in working with Zebu/Palladium emulators is a plus
• Knowledge of ASIC flow, DV flow, SoC Architecture and debugging
• Expertise in Verilog, System Verilog, VHDL languages.
• Expertise in scripting and programming languages.

Contact:
Jyoti.vimal@Infineon.com

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