Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks
Write testbenches, functional coverage models, and assertions
Run simulations, analyze failures, and debug both RTL and testbench issues
Collaborate with design, architecture, and analog teams on block-level and top-level verification
Verify high-speed SerDes IP used in PCIe, Ethernet, and other industry-standard interfaces
Requirements
- BSc in Electrical Engineering, Computer Engineering, or equivalent
- 0-5 years of experience in digital design or verification (internships, academic projects, or industry)
- Working knowledge of SystemVerilog and basic familiarity with UVM concepts
- Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing
- Strong analytical and debug mindset - you enjoy getting to the bottom of a problem
- Good communication skills in English (spoken and written)
- Candidates should preferably be able to reside in Iași
Core Competencies
Demonstrates expertise in developing and maintaining SystemVerilog/UVM verification environments, with a strong foundation in digital design principles and the ability to analyze and debug complex issues. Effective collaboration with cross-functional teams and strong communication skills in English are essential.
Highest-signal resume keywords
- SystemVerilog
- UVM
- Digital Design Fundamentals
- Analytical Mindset
- Communication Skills
Hard Skills
- Testbench Development
- Functional Coverage Models
- Assertions
- Simulation Analysis
- Debugging RTL Issues
- Synchronous Logic
- Finite State Machines
- Pipelining
- Clock Domain Crossing
Soft Skills
- Analytical Thinking
- Problem Solving
- Collaboration
Certifications & Qualifications
- BSc in Electrical Engineering
- BSc in Computer Engineering
Industry Keywords
- SerDes
- PHY Blocks
- PCIe
- Ethernet
- Verification Environment
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Design Verification Engineer Arbeitgeber: Jobtailor
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