Digital Design Engineer, UK, CH

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.We are actively seeking for a Digital Design EngineerLocation: Lausanne (St-Sulpice), SwitzerlandResponsibilityConcept definition, analog to digital interface specificationRTL design with basics of Dft and IP verificationLogic synthesis, Timing analysis – desiredClose interaction with Verification engineers, Analog/Mixed signal designersDevelop block level specifications of very high-speed digital circuits that meet key performance targets based on system level requirementDesign and verification of very high-speed digital circuitsSupport for post-silicon lab bring-up, debug, characterization and productizationAnalysis and understanding of high-speed serial protocols (e.g., USB4, PCIe)Analog/digital interface specification in close cooperation with analog/mixed-signal designersValidation and bring-up of chips in the labClose interaction with verification and physical implementation engineers to verify circuit functionality and compliance with area, timing, and power requirementsSupport and interact with customers on requirements, design specifications, performance results and product deliverySupport IP and chip level integrationManage workload and schedules and report to internal management team and external customersRequired Experience5-10 years’ experience in digital design of key circuits in multi-Gigabit serial data-link transceivers, DDR and low power high performance modern memory interfaces and experience in the semiconductor industryStrong technical background in design of high-speed digital circuits in deep-submicron CMOS technologiesProven experience in complex digital design and verification of data processing systemsProven experience in design and verification of complex regulation systems (configuration, calibration, and dynamic adaption)Experience in industry standard design EDA tools for design, simulation, and verificationExperience in digital high-speed blocks, CMOS High Speed interface competence would be a preferenceExposure to the Cadence toolsetExperience with multi-Gigabit serial data transceivers is highly desirableExperience with analog/digital control interfaces is valuableRequired SkillsStrong interest in the design of digital circuits and blocks for multi-Gigabit serial ana parallel data-link transceivers, DDR and low power high performance memory and communication interfacesStrong scripting and tool setup skillStrong analytical skills to translate system-level requirements into designSelf-motivated, with strong sense of ownership and responsibility. Good communicator and team playerRTL coding skills, CDC and Linting knowledgeUnderstanding of verification tools and methodologies is an advantageKnowledge of synthesis, STA and signal processing techniques is an advantageAdvanced knowledge of high-speed and low-power design techniques and high-speed serial protocolsScripting (Python preferred) and tool setup skillsRequired EducationProven experience and/or Masters or Ph.D. in E.E., Communications or other relevant fieldsMSc in electronics/electrical engineering (equivalent or Website #J-18808-Ljbffr