Eda/Cad Engineer

At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient . Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

We are actively seeking an EDA/CAD Engineer, based either in UK (Cambridge or Reading), Switzerland (St-Sulpice), or India (Hyderabad or Bangalore)

Department: RnDKey Responsibilities

• Manage and maintain an integrated analog/digital EDA environment, including installation, configuration, and support of tools such as Cadence Virtuoso, Synopsys platforms, and Siemens Calibre/AFS.

• Flow development & automation: design, automate, and validate robust CAD flows for simulation, physical verification, parasitic extraction, and reliability analysis.

• Methodology support: provide expert guidance to analog and digital design engineers;

  troubleshoot toolissues;

  optimize design methodologies for performance and quality.

• Vendor management: serve as the primary technical contact with EDA vendors to resolve complex issues, drive bug fixes, and evaluate new versions/features.

• PDK installation & support: contribute to installation, qualification, and deployment of PDKs for advanced technology nodes.

• Design enablement: create and maintain clear documentation, training materials, and scripts so teams can use tools and flows effectively.

• Continuous improvement: proactively identify bottlenecks and implement solutions that improve productivity, accuracy, and turnaround time.

Skills

• Strong programming skills: Shell, Python, Perl, Tcl, SKILL;

  ability to develop simple GUIs;

  Make-based build automation.

• Solid understanding of the full chip-design lifecycle and digital, analog, and mixed‑signal IC design flows.

• Strong communication and interpersonal skills;

  collaborates effectively with engineering teams and vendors.

• Excellent problem‑solving skills with the ability to prioritize and manage multiple tasks in a fast‑paced environment.

• Proficient in EDA/CAD flow development while balancing stakeholder needs (quality, schedule, and compute efficiency).

• Ability to quickly learn, understand, maintain, and enhance complex software design tools.

Experience

• Bachelor or Master of Science Degree, in Electrical Engineering, Computer Engineering, Computer Science.

• 10+ years in an EDA/CAD engineering supporting both analog and digital IC design teams.

• Proven experience at advanced technology nodes and associated PDKs. Practical knowledge of industry-standard methodologies, tool licensing, revision control, and release management.

• Hands-on expertise with key tools across: Analog/RF (Cadence Virtuoso Schematic/Layout, ADE, Spectre/APS/AFS), Physical Verification (Siemens Calibre;

  Cadence Pegasus),Parasitic Extraction (Cadence Quantus), and Digital Implementation (Synopsys Design Compiler & IC Compiler II;

  Cadence Innovus).

• Proven experience at advanced technology nodes and associated PDKs.

• Practical knowledge of industry-standard methodologies, tool licensing, revision control, and release management.

• Deep data management experience (Git, Cliosoft) enabling consistent, flexible multi‑project/multi‑discipline flow setup and database tagging.

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