Experience: 5–7 Years
Location: Germany
Domain: Semiconductor / Memory Design
Role Overview
We are looking for a Memory Layout Engineer with 5–7 years of hands‑on experience in memory layout design, specifically on lower technology nodes. The role involves layout development, verification, and close collaboration with design and verification teams.
Key Responsibilities
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Perform memory layout design for SRAM / memory blocks
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Work on lower technology nodes (mandatory)
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Ensure layout meets DRC, LVS, and density requirements
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Optimize layout for performance, power, and area (PPA)
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Collaborate with circuit design and verification teams
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Support tape‑out activities and resolve layout‑related issues
Mandatory Skills
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5–7 years of experience in memory layout engineering
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Strong experience in lower nodes (mandatory)
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Hands‑on with DRC/LVS closure
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Good understanding of semiconductor layout fundamentals
Good to Have
- Experience with advanced memory architectures
- Exposure to multiple process nodes
- Strong communication and teamwork skills
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