Senior Digital IC Design Engineer

Job Title: Senior Digital IC Design EngineerPosition: Full time, permanentLocation: Biel, SwitzerlandSalary Range: 115K CHF negotiableClient Information:You will work closely with colleagues in both the IC Design and Product Definition teams to provide solutions required for the digital elements of the mixed signal products developed. In addition, you will work in developing behavioural models to help accelerate simulation or form part of system emulation.Responsibilities:Develop functional digital blocks and contribute to complete mixed-signal ASICs, from definition to full production maturity.Collaborate with the Product Definition team on feasibility studies, product architecture definition, and digital block design for FPGA emulation.Perform RTL design in SystemVerilog, ensuring all digital functions meet specification requirements.Create comprehensive block-level testbenches to verify all digital blocks thoroughly.Develop behavioural models and top-level testbenches for system-level function and production test verification, including regression testing.Carry out digital synthesis, applying appropriate physical constraints to meet Power, Performance, and Area (PPA) requirements.Define and implement DFT architecture, including scan insertion, ATPG, and test point insertion to achieve desired test coverage.Design digital layout floorplans, oversee place-and-route processes, and ensure post-layout timing closure.Prepare all necessary design documentation and actively participate in design reviews.Contribute to product-level verification and validation plans.Support silicon evaluation and product validation activities in collaboration with Product, Quality, and Test Engineering teams, up to production ramp-up.Drive improvements in Technology Process and Design Website or PhD in Electronics Engineering or a related field.Minimum of 5 years’ experience in digital IC design using standard cell libraries.Strong knowledge and understanding of best-practice digital design methods.Proven experience executing designs via a fully synthesized digital design flow, including RTL and logic synthesis.Proficient in the SystemVerilog standard and scripting languages such as TCL.Familiar with using constraints and the automatic place-and-route flow for physical design.Understanding the importance of production testing and experience with design methods to maximize test coverage, such as scan insertion.Experience with design techniques for optimizing digital power consumption.Skilled in debugging digital functions in a lab environment using appropriate test equipment (e.g., mixed-signal oscilloscopes).Demonstrated ability to produce accurate and complete documentation. #J-18808-Ljbffr