Digital Designer / RTL Design Engineer Es kann sein, dass sich eine große Anzahl von Bewerbern auf diese Stelle bewirbt. Schicken Sie daher Ihren Lebenslauf und Ihre Bewerbung so schnell wie möglich ab. Duration: November 2026 - September 2027 Location: Remote with ramp up and some onsite visits We are seeking an experienced Digital Designer / RTL Design Engineer to support the design and development of low-power, multi-clock-domain digital blocks within a distributed engineering team. The engagement is expected to run from early November 2026 through September 2027. An initial 1-2 week ramp-up/onboarding period at the beginning of the assignment would be preferred. There may also be a requirement for one or two short on-site meetings during the engagement, potentially around the mid-term/design review. These would be one-off visits rather than ongoing travel requirements. The engineer will be responsible for the design, implementation, integration, and sign-off support of low-power, multi-clock-domain digital blocks. Write the block specification in DOORs based on the system architecture and requirements. Participate in the microarchitecture definition, architecture refinement. Participate in design reviews. Develop low-power RTL design in VHDL/System Verilog according to the block specification, including block integration to the system. Emphasis in the project is on the aggressive application of low-power synchronous design technique and area reduction. Optimize the design for power, area, timing, and maintainability. Cooperate with the Verification team, do block debugging, specify corner cases for testcases and verification, support the coverage closure. Synthesize the block in Fusion Compiler including SDC writing, cooperate with the backend team Execute and debug LINT, CDC analysis, Formality Logical Equivalence Checking. Required competencies Team player, strong communication skills in English (remote work in a distributed team), ability to drive issues to closure. System-level thinking, ability to choose the right trade-off. Ability to develop well-readable, reusable, and parametrized RTL code. SystemVerilog, VHDL RTL - sound knowledge. xhdzyng Low power digital design, experience with multiple clock domain designs, CDC techniques PSL, SVA assertions - applications in the digital design Fusion Compiler scripting, work in, constraining, SDC, STA review and block optimization DFT-friendly digital design, basics of the RTL DFT, functional testing, Formality/LEC. Experience with serial intefaces (SPI, I2C, I3C) (optional, but would be very useful to have) Digital design for signal processing (optional) GIT, SVN Jasper Gold tools - CDC (+RDC), LINTing (optional) DOORs - requirement management (optional) Python (optional) #J-18808-Ljbffr
Digital Designer / RTL Design Engineer Arbeitgeber: microTECH Global LTD
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