Digital Verification Engineer Lesen Sie bitte die vollständige Beschreibung und bewerben Sie sich sofort, wenn Sie sicher sind, dass Sie alle Anforderungen erfüllen. Duration: November 2026 – September 2027 Location: Remote with ramp up and some onsite visits The engagement is expected to run from early November 2026 through September 2027. An initial 1–2 week ramp-up/onboarding period at the beginning of the assignment would be preferred. There may also be a requirement for one or two short on-site meetings during the engagement, potentially around the mid-term/design review. These would be one-off visits rather than ongoing travel requirements. The engineer will be responsible for developing and maintaining block- and subsystem-level verification environments, executing verification plans, managing regressions, and driving verification closure. Participate in creating verification plans, subblock verification strategy, create verification scenarios. Participate in creating system level testbench and integration of subblocks into top level test bench. Create functional coverage models, including RNM models. Create verification blocks/environments for design blocks. Write sequences/test cases. Create assertion modules for checking proper behavior of modules. Participate in code reviews and test bench architecture reviews. Cooperate with design team on identifying proper scenarios and corner cases, identifying ambiguities and holes in specification. Do the code coverage closure. Do debugging and reporting bugs to the design team on the RTL as well as back-annotated gate level. Required competencies Team player, strong communication skills in English (remote work in a distributed team), ability to drive issues to closure. Advanced knowledge od SystemVerilog (core language, constraints syntax, functional coverage syntax). Knowledge of SystemVerilog Assertions, PSL Assertions. Knowledge of UVM and TLM, and OOP design patterns (SystemVerilog). Knowledge of constrained-random testing. Experience with Cadence Xcelium. Experience with regressions management and vPlan creation and regression post-processing in Cadence vManager. Understanding RTL code coverage principles and functional coverage principles: definition, triggering, sampling. Knowledge of serial protocols - SPI, I2C, and I3C. Understanding structure of UVC/VIP blocks - UVM basic building blocks. Experience with UVM RAL. System level thinking, understanding SOC test bench structure, interconnecting building blocks into system level test bench. Experience with modeling of analogue blocks, RNM models. Experience with the debugging of the back-annotated gate level netlist, Understand and apply principles of readable code. xhdzyng Ability to report bugs properly with necessary and straightforward context for easy reproduction. Experience with GIT - proper branching, working with pull requests, #J-18808-Ljbffr
Digital Verification Engineer - Contract Arbeitgeber: microTECH Global LTD
Als Arbeitgeber bieten wir Ihnen die Möglichkeit, in einem dynamischen und innovativen Umfeld zu arbeiten, das auf kontinuierliches Lernen und persönliche Entwicklung setzt. Unsere Unternehmenskultur fördert Zusammenarbeit und Kreativität, während wir gleichzeitig attraktive Benefits wie flexible Arbeitszeiten und Weiterbildungsmöglichkeiten anbieten. In dieser Rolle als Senior Salesforce Developer haben Sie die Chance, an spannenden Projekten zu arbeiten und Ihre Expertise in einem wachsenden Team einzubringen, das die Zukunft unserer CRM-Landschaft gestaltet.
