In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and PD design teams, with a critical impact on delivering best in class PHY designs. You will be required to do designs of best in class PHY design.
Description:
Core Responsibilities:
- Participate in the architecture of next generation DDR PHY.
- Design DDR PHY from architecture to micro-architecture.
- RTL implementation of the micro-architecture.
- Participate in clearly defining specification, testing and verification of the DDR PHY design.
- Work closely with CAD, PD teams to implement RTL design into GDS.
- Run various design verification flow at PHY level and provide guidelines to other designers.
- Participate in establishing CAD and design methodologies for correct by construction designs.
- Assist in flow development for PHY integration.
Qualifications:
The ideal candidate will have 5+ years of DDR PHY Design experience on high performance, low power SOC designs.
- Knowledge about industry standards and practices in PHY Design, including RTL writing, verification tools of RTL.
- Experience in developing and implementing DDR PHY.
- Solid understanding of all aspects of PHY construction, integration, and physical design.
- Knowledge of basic SoC architecture and HDL languages like Verilog to collaborate with the design team for timing fixes.
- Knowledge of circuit design and transistor operation is a plus.
- Power user of industry standard RTL design & synthesis tools.
- Solid understanding of scripting languages such as Perl / Tcl.
- Working knowledge of extraction and STA methodology and tools.
- Good understanding of design methodology to debug issues at PHY level.
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Kontaktperson:
Microtech Global Ltd HR Team