Senior Digital ASIC Design Engineer Synthesis (m/f/d)

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

Böblingen Vollzeit 60000 - 80000 € / Jahr (geschätzt) Kein Homeoffice möglich
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Auf einen Blick

  • Aufgaben: Entwickle komplexe digitale ASICs und arbeite an innovativen Testlösungen.
  • Unternehmen: Globaler Marktführer in automatisierten Testsystemen für die Halbleiterindustrie.
  • Vorteile: Flexible Arbeitszeiten, 30 Urlaubstage, attraktives Gehalt und umfangreiche Schulungsangebote.
  • Weitere Informationen: Dynamisches Team mit hervorragenden Entwicklungsmöglichkeiten und einem ergonomischen Arbeitsumfeld.
  • Warum dieser Job: Gestalte die Technologien von morgen und arbeite an spannenden Projekten.
  • Qualifikationen: Abschluss in Elektrotechnik und Erfahrung in digitalem Design und RTL-Codierung.

Das prognostizierte Gehalt liegt zwischen 60000 - 80000 € pro Jahr.

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

We enable tomorrow's technology—a global leader in automated test systems for the semiconductor industry.

  • Your Responsibilities
  • Join a global engineering team at the heart of Advantest’s IC test solutions.
  • Help create the key technologies that enable the next generation of semiconductor testing.
  • Work on complex mixed‑signal ASICs used in Advantest’s testers, taking digital modules and subsystems from first concept to silicon.
  • Collaborate closely with system architects and design engineers.
  • Generate constraints for synthesis of IP blocks and top‑level chip integration.
  • Analyze critical paths, control power consumption, solve challenging technical problems, and deliver high‑quality results on schedule and at scale.
  • Develop architecture for CMOS designs and design and RTL coding of digital and full‑custom modules.
  • Verify at module and chip level, generating test plans and cases.
  • Document implemented functionality.
  • Generate constraints and synthesize IP blocks and chip top level.
  • Analyze timing and power consumption, support floor‑planning and physical design.
  • Work closely with design partners.
  • Your Qualifications
  • University degree, diploma, or BS in Electrical Engineering.
  • Background in digital design (SOC), ASIC design methodologies, and silicon development cycle.
  • Experience in RTL coding with Verilog and System Verilog.
  • Experience with standard digital simulation tools.
  • Basic knowledge of UNIX or Linux environment and programming languages.
  • Strong technical communication, teamwork, and problem‑solving skills.
  • English language proficiency.
  • Our Offer
  • Flexible and trust‑based working hours, 30 vacation days plus optional additional days, mobile working, and part‑time models for extended absences.
  • Attractive salary with a bonus program, subsidies, discounts, and other offerings (e. g., bike leasing).
  • Structured onboarding programs, mentoring, technical and soft‑skill trainings, language courses, and knowledge sessions.
  • Ergonomic working environment with sports and fitness options and events (e. g., Global Challenge) and health days.
  • Company pension scheme, comprehensive insurance coverage, and emergency support.
  • Contact
  • If you have any questions, you can contact Alena Nicolai at

+49 (0) 7031.204.8380 .

#J-18808-Ljbffr

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Kontaktdaten:

MR Jobfinder GmbH Recruiting-Team

Wir glauben, dass du diese Fähigkeiten brauchst, um Senior Digital ASIC Design Engineer Synthesis (m/f/d) mit Bravour zu bestehen

Digital Design
ASIC Design Methodologies
Silicon Development Cycle
RTL Coding
Verilog
SystemVerilog
Standard Digital Simulation Tools