Coherent Systems Architect - Mixed Signal AFE development

Coherent RF Architect – Job Description

We are seeking a hands‑on Coherent RF Architect to lead silicon bring‑up, validation, and production test development for a mixed‑signal Analog Front‑End (AFE) featuring high‑speed DACs, ADCs, PLL/clocking, and the RF electrical interface to the Transmitter and Receiver Optical Sub‑Assembly (TROSA) used in the optical coherent pluggable.

The role owns end‑to‑end AFE characterization, from bench measurement and automation through correlation to simulation test coverage.

How You Will Contribute And What You Will Learn

Key Responsibilities

• Silicon Bring‑up & Debug
• Own first‑silicon bring‑up for DAC/ADC/PLL blocks: power‑up sequencing, register access, clock tree bring‑up, and initial functional validation.
• Debug mixed‑signal issues across domains (clocking, analog biasing, digital control, interfaces, and test modes).
• Create debug playbooks and known‑good procedures to accelerate lab triage and cross‑team communication.
• Full AFE Characterization (Bench + Automation)
• DAC: SFDR, IMD, THD, SNR, ENOB, spurs vs. output amplitude, output frequency, sampling frequency, temperature, supply, and code format; static linearity where applicable.
• ADC: SNR, ENOB, SFDR, interleaving mismatch (offset/gain/timing), harmonic/spurious behavior, clock sensitivity.
• PLL/Clocking: phase noise, integrated jitter, spur analysis, jitter transfer/tolerance where relevant to the system.
• AFE‑level metrics: frequency response, passband ripple, impedance/termination impact, crosstalk, noise coupling, and sensitivity to board/connector effects.
• Design experiments for PVT sweeps and margin analysis; develop guard‑banding strategies aligned to production realities.
• RF Characterization of TROSA
• Characterize RF electrical behavior of the Transmitter and Receiver Optical Sub‑Assembly, including bandwidth, frequency response, impedance matching, insertion and return loss, gain, noise figure (where applicable), and linearity.
• Work closely with photonics, Si Ge IC, and module teams to correlate electrical AFE performance to optical metrics.
• Support electro‑optical (E/O) and opto‑electrical (O/E) RF validation for coherent transmit and receive chains.
• Measurement Infrastructure & Data Analytics
• Build and maintain automated measurement systems using Python and standard instrument control (SCPI/Py VISA).
• Use robust data practices: versioned test scripts, metadata capture, calibration traceability, and reproducible analysis notebooks.
• Create dashboards/reports summarizing performance trends, correlations, and anomalies.
• Cross‑Functional Collaboration & Requirements
• Work with design teams to define test hooks, observability, calibration registers, and design‑for‑test requirements for analog blocks.
• Define measurable acceptance criteria aligned to coherent system requirements.
• Collaborate closely with Analog/RF design, Si Ge IC teams, DSP, Signal Integrity (SI), photonics, module, and manufacturing teams.
• Required Qualifications
• Ph. D. in Electrical Engineering or Applied Physics with experience in mixed‑signal silicon test/validation/characterization, high‑speed electronics or systems.
• Strong fundamentals in high‑speed electronics and practical experience with test equipment such as high‑bandwidth oscilloscopes, phase noise analyzer, spectrum analyzer, VNA.
• Experience characterizing high‑speed RF and mm‑wave interconnects, amplifiers, and components.
• Solid automation skills in Python including data pipelines and plotting.
• Ability to read schematics, understand board‑level effects, and debug signal integrity/power integrity interactions.
• Comfortable in a fast‑moving lab environment: hands‑on probing, rework coordination, fixture bring‑up.
• Preferred Qualifications
• Experience with optical coherent systems and coherent transceiver architectures.
• Experience with MZ modulator drivers (MZMD) and TIAs in coherent links.
• Experience with high‑speed data converters, interleaved ADCs, and calibration techniques.
• #J-18808-Ljbffr