DFT Digital Design Engineer (f/m/d)

• Scope of Responsibilities/Expectations
• Support the implementation and integration of Design for Test (Df T) for complex So C and semiconductor products.
• Participate in Df T implementation activities including Scan, MBIST, Boundary Scan (JTAG), Logic BIST, test compression, ATPG pattern generation, fault simulation, and Df T verification.
• Assist in the development, verification, validation, and integration of test structures throughout the So C design cycle to achieve manufacturing test coverage, silicon quality, and product reliability goals.
• Perform Df T-related checks, analyze fault coverage and test results, and support debug of Df T issues during design, verification, silicon bring-up, characterization, and yield improvement activities.
• Work closely with Design, Verification, Physical Design, Product Engineering, and Test Engineering teams to support Df T integration, validation, and product development.
• Assist in developing scripts and automation solutions to improve Df T productivity, flow efficiency, and methodology execution.
• Create, maintain, and improve Df T documentation, implementation guidelines, methodologies, design standards, and lessons learned.
• Demonstrate continuous learning and contribute to the advancement of Df T methodologies, semiconductor test technologies, and best practices.
• Perform assigned Df T tasks under the guidance and mentorship of senior engineers.
• Specific Knowledge/Skills
• Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related field.
• Good understanding of digital design fundamentals, including combinational and sequential logic, finite state machines, computer architecture fundamentals, and RTL design using Verilog/System Verilog.
• Basic understanding of CMOS design principles, semiconductor manufacturing concepts, ASIC/So C design flows, and manufacturing test methodologies.
• Exposure to or basic understanding of Df T concepts including scan architecture, ATPG, fault models, MBIST, Boundary Scan (IEEE 1149.1/JTAG), Logic BIST fundamentals, and test compression techniques.
• Familiarity with simulation methodologies, debugging techniques, waveform analysis, and Df T verification flows.
• Understanding of timing, synthesis, and physical design concepts.
• Familiarity with Linux/Unix environments and exposure to scripting languages such as Python, Tcl, Perl, or Shell.
• Familiarity with EDA tools used for digital design, verification, implementation, and Df T flows.
• Strong analytical, logical reasoning, debugging, and problem-solving skills with the ability to break complex problems into manageable components.
• Self-motivated, detail-oriented, and committed to quality, execution excellence, and continuous improvement.
• Excellent written and verbal communication skills.
• Ability to work effectively in cross-functional teams, manage multiple priorities, learn through technical mentorship, and collaborate in a dynamic development environment.
• Strong curiosity, willingness to learn, and passion for semiconductor and test technologies.

Please note: The successful candidate may/will be responsible for security related tasks.

The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.

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