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- Aufgaben: Join us as a Design Verification Engineer to create and execute test plans for cutting-edge designs.
- Arbeitgeber: Scadea Solutions connects top talent with leading companies across diverse industries worldwide.
- Mitarbeitervorteile: Enjoy a full-time role with opportunities for growth and collaboration in a dynamic environment.
- Warum dieser Job: Be part of a team that ensures high-quality designs and contributes to innovative technology solutions.
- Gewünschte Qualifikationen: 5+ years in ASIC/SOC verification with hands-on HVL expertise is a must.
- Andere Informationen: Experience with git, VCS, and cross-site teamwork is a plus!
Das voraussichtliche Gehalt liegt zwischen 48000 - 84000 € pro Jahr.
Scadea Solutions is a global talent acquisition and executive search company. We work exclusively with some of the most reputed and admired clients across various sectors and geographies. This is a very urgent role.
Job Description
Role: Design Verification Engineer
Location: Allentown, PA
Duration: Full-time
Description:
As a design verification engineer, you will be responsible for understanding expected design functionality, developing test plans, and functional validation tests to verify the system will meet design requirements. You will be working closely with design engineers, architects, and other team members to ensure high-quality test plans and flawless test plan execution.
Minimum Qualifications:
- 5+ years of related industry experience in ASIC/SOC verification
- Must have hands-on experience and expert level knowledge on HVL based verification
Duties:
- Verification plan creation for various blocks
- Develop the SoC/Subsystem Test case suite in various stages like RTL, GLS releases.
- Integrate System Verilog, OVM Test bench components like Scoreboard, Monitors, and Bus Function Models.
- Develop System Level Scenarios for full Chip.
- Debug the complex chip simulations and deliver bug-free chips.
- Perform Code and functional coverage analysis for Various Subsystems.
- Meet Quality requirements before various RTL release stages.
Nice to have:
- Working experience of git version management tool
- Working experience on VCS, Questa CDC, Verdi
- Ability to deliver high-quality output against deadlines and work effectively in a cross-site team environment
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Design verification Engineer Arbeitgeber: Scadea Solutions Inc
Kontaktperson:
Scadea Solutions Inc HR Team
StudySmarter Bewerbungstipps 🤫
So bekommst du den Job: Design verification Engineer
✨Tip Number 1
Make sure to familiarize yourself with the latest trends and technologies in ASIC/SOC verification. This will not only help you understand the expectations of the role but also allow you to engage in meaningful conversations during interviews.
✨Tip Number 2
Network with professionals in the field of design verification. Attend industry conferences, webinars, or local meetups to connect with others who may have insights into the hiring process at Scadea Solutions.
✨Tip Number 3
Brush up on your hands-on experience with HVL based verification tools. Being able to demonstrate your expertise in System Verilog and OVM Test bench components can set you apart from other candidates.
✨Tip Number 4
Prepare to discuss specific examples of your past work related to verification plan creation and debugging complex chip simulations. Having concrete examples ready will showcase your problem-solving skills and experience effectively.
Diese Fähigkeiten machen dich zur top Bewerber*in für die Stelle: Design verification Engineer
Tipps für deine Bewerbung 🫡
Understand the Role: Make sure you fully understand the responsibilities and qualifications required for the Design Verification Engineer position. Tailor your application to highlight your relevant experience in ASIC/SOC verification and HVL based verification.
Highlight Relevant Experience: In your CV and cover letter, emphasize your 5+ years of industry experience, particularly focusing on your hands-on experience with verification plans, test case suites, and debugging complex chip simulations.
Showcase Technical Skills: Clearly outline your technical skills related to System Verilog, OVM Test bench components, and any experience with tools like VCS, Questa CDC, and Verdi. Mention your familiarity with git version management as a nice-to-have skill.
Craft a Strong Cover Letter: Write a compelling cover letter that not only summarizes your qualifications but also demonstrates your passion for the role and how you can contribute to the team. Make sure to express your ability to deliver high-quality output against deadlines.
Wie du dich auf ein Vorstellungsgespräch bei Scadea Solutions Inc vorbereitest
✨Understand the Role
Make sure you have a clear understanding of the responsibilities of a Design Verification Engineer. Familiarize yourself with ASIC/SOC verification processes and be ready to discuss your experience in developing test plans and executing them.
✨Showcase Your Technical Skills
Be prepared to demonstrate your hands-on experience with HVL based verification. Discuss specific projects where you integrated System Verilog, OVM Test bench components, and how you approached debugging complex chip simulations.
✨Prepare for Behavioral Questions
Expect questions about teamwork and collaboration, especially since you'll be working closely with design engineers and architects. Have examples ready that showcase your ability to deliver high-quality output under deadlines in a cross-site team environment.
✨Ask Insightful Questions
Prepare thoughtful questions about the company's verification processes, tools they use like git, VCS, or Questa CDC, and their expectations for the role. This shows your genuine interest in the position and helps you assess if it's the right fit for you.
