Student Project - Proof of Concept for JTAG driven DFT implementation

Proof of Concept for JTAG driven DFT implementation

Project Description

Current DFT (scan) implementation requires several external control pins that can be difficult to allocate in low pin count implementation. The addition of MBIST to the test mode introduces even more requirements for additional control pins to control test mode in an efficient way without using the CPU core to handle this.

The goal of this internship is to test the implementation of register-controlled test mode management using a JTAG interface to write in the test registers. Define multiple test modes via JTAG and verify mode selection in simulations. Although JTAG introduces extra pins, most designs contain a JTAG interface that can also be used for DFT test modes.

The project will be divided into the following steps:

1. Training on DFT implementation in an existing design under the control of a DFT expert.
2. Documentation around JTAG controlled DFT implementation.
3. Define and make the strategy reviewed on the existing DFT strategy.
4. Implement the solution and compare runtime and pin count compared to the original pin controlled implementation.
5. Document the job done with pros & cons.

We offer:

• An exciting work environment where you will be sitting side-by-side and interacting with our DFT and Implementation expert within the SoC initiative team.
• Working in a multinational team with a great atmosphere.
• A place where your internship matters and will live on after you leave.

Internship Period is foreseen from: 1st February – 31st July.

What you should bring along:

• Student in Electrical Engineering or Microelectronic system design with basic knowledge of semiconductor and digital design.

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