Staff Project Engineering Manager

About the Role

We are looking for a Staff Project Engineering Manager (PEM) to lead the end-to-end delivery of Mixed-Signal IP and So C/ASIC programs — from concept through customer tape-out and silicon validation.

This role blends deep semiconductor technical knowledge with organizational leadership, requiring someone equally comfortable coordinating analog macro deliverables with circuit designers, tracking an RTL-to-GDS schedule with physical design teams, and presenting program status to enterprise customers.

As a Staff-level PEM, you are not just a schedule tracker — you are a technical partner to the engineering team and a credible representative to customers.

You will anticipate risks that only a seasoned semiconductor engineer would recognize, drive cross-functional alignment across analog design, digital RTL, verification, physical design, and validation teams, and ensure that commitments to customers are made and kept with engineering rigor behind them.

Key Responsibilities

• Program & Project Management Own end-to-end program management for Mixed-Signal IP and So C/ASIC projects: scoping, scheduling, milestone tracking, risk management, and customer delivery.

Build and maintain detailed program schedules spanning analog macro design and characterization, RTL design, verification, physical implementation (RTL-to-GDS), and silicon validation phases — capturing interdependencies across all disciplines.

• Identify schedule risks, dependency conflicts, and resource gaps early — driving mitigation plans in partnership with engineering leads and management.
• Track deliverables across multiple concurrent R&D teams, ensuring cross-team dependencies are visible, communicated, and resolved proactively.
• Manage change requests from internal teams and customers: triage technical feasibility, assess schedule and resource impact, and drive to clear decisions.
• Technical Engagement & Design Flow Oversight
• Leverage deep semiconductor background — spanning Mixed-Signal IP, analog macro design, Front-End RTL, So C, and ASIC — to engage meaningfully with R&D teams on design decisions, trade-offs, and blocking issues.
• Coordinate analog macro programs end-to-end: working with analog designers on schematic, simulation, and layout milestones; tracking PVT characterization schedules; and managing handoff of characterized macros (PLLs, Ser Des PHYs, I/O buffers, LDOs, or similar) to integration teams.
• Maintain solid understanding of the full RTL-to-GDS flow — RTL design, synthesis, DFT, functional verification, place-and-route, sign-off, and tape-out — enabling credible schedule and risk assessment at each phase.
• Understand the interaction between analog macro integration and digital implementation: floorplan constraints, power domain boundaries, interface timing, and mixed-signal verification handoffs.
• Participate in design and verification reviews, contributing a program perspective on scope, schedule implications, and customer commitment alignment.
• Support silicon validation planning, coordinating test content, bring-up milestones, and customer evaluation timelines in conjunction with validation engineering teams.
• Customer & Stakeholder Management
• Serve as the primary program interface for external customers on Mixed-Signal IP and So C deliveries — communicating program status, schedule updates, deliverable content, and issue resolution with clarity and confidence.
• Build strong customer relationships by combining technical credibility with responsiveness, proactive communication, and a track record of delivery.
• Represent the product line internally and externally, translating between customer needs and engineering realities without overpromising or underdelivering.
• Coordinate pre-sales and post-sales technical support in partnership with Sales, Marketing, and IP Program Management teams — providing engineering context that enables informed customer decisions.
• Manage customer-facing design reviews, milestone acceptance, and IP delivery packages, ensuring documentation, quality, and content meet customer and contractual requirements.
• Cross-Functional Coordination
• Drive alignment across analog design, RTL, CAD/EDA, verification, physical design, validation, and product management teams throughout the program lifecycle.
• Facilitate weekly program reviews, risk forums, and escalation meetings — maintaining a single source of truth on program status and actions.
• Coordinate with foundry and packaging partners on tape-out logistics, PDK readiness, and silicon delivery timelines.
• Partner with quality management and IP program management teams to ensure programs comply with quality system processes, IP release criteria, and customer quality requirements.
• Support resource planning discussions with engineering management, providing data-driven input on headcount needs, schedule trade-offs, and program prioritization.

Qualifications

• Required
• 5–10 years of experience in semiconductor development, including meaningful involvement in program or project management of Mixed-Signal IP, So C, or ASIC programs.
• Strong technical foundation spanning both analog macro design and digital RTL-to-GDS flows — with sufficient depth to assess risks, review schedules, and engage credibly with engineers across both domains.
• Demonstrated experience coordinating analog macro deliverables (circuit design, layout, PVT characterization, and integration handoff) within a larger So C or IP program context.
• Demonstrated experience managing complex, multi-team semiconductor programs from specification through customer delivery, including tape-out coordination.
• Proficiency with project management tools and methodologies (Jira, MS Project, or equivalent); experience maintaining program schedules and risk registers for engineering organizations.
• Proven track record of direct customer engagement — presenting program status, managing expectations, and resolving technical and schedule issues at the enterprise level.
• Solid understanding of quality management system processes applicable to IP and semiconductor product delivery (ISO 9001, IATF 16949, or similar).
• BS in Electrical Engineering, Computer Engineering, or related technical discipline.

What We Offer

• Competitive total compensation: base salary, equity, and performance bonus.
• High-visibility staff-level role at the intersection of analog, digital, and program leadership.
• Opportunity to shape program management methodology and best practices across a growing global silicon organization.
• Collaborative, technically rigorous culture where program managers are respected as engineering partners, not administrators.
• Comprehensive benefits: medical, dental, vision, 401(k) match, and flexible PTO.
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