ppDesign and ship high-performance, low-power SRAM and custom-digital sub-systems that sit at the core of our compute-in-memory technology. You will own architecture, circuit implementation, verification, and silicon correlation for advanced nodes, down to sub-5 nm, thereby improving both the efficiency and robustness of our macros. Expect hands‑on work on memory periphery and datapath interfaces, as well as close collaboration with layout, digital, backend, DFT, and test teams. /ph3bWhat you’ll do /b /h3ulliDesign and verify embedded SRAM or custom digital blocks, including caches, register files, datapath, and datapath‑adjacent interfaces. /liliOptimize for PPA on advanced nodes: variation and stability closure, corners and Monte Carlo, leakage and dynamic power reduction. /liliIntegrate for product: define clean digital boundaries and timing budgets so blocks drop into a digital‑on‑top flow without surprises. /liliPlan and run silicon correlation: bring‑up, characterization benches, analysis of ATE data, clear errata, and fixes. /liliPartner with layout early on floorplan, guarding, shielding, routing topology; review extraction and resolve EM/IR issues. /liliImprove methods with scripts for characterization, regression, and reporting (Python or Tcl), and contribute specs, checklists, and reusable collateral. /li /ulh3bOutcomes (first 18 months) /b /h3ulliTape‑in and silicon of at least one SRAM or custom‑memory sub‑system that meets spec across PVT, with signed correlation and test reports. /liliA measurable efficiency gain on an existing macro or block you optimize, documented with before/after data. /liliA reusable design and verification kit (models, plans, scripts, checklists) that shortens the following variant’s cycle time. /li /ulh3bRequirements /b /h3ulliMS or PhD in Electrical or Computer Engineering and 5+ years in custom digital, analog, or SRAM design. /liliProven ownership through complete design cycleson sub‑blocks. /liliStrong understanding of high‑performance and low‑power circuit design on FinFET nodes, including bitcell stability and periphery trade‑offs. /liliAbility to frame and communicate clear interfaces and constraints across teams; organized, self‑directed, delivery‑oriented. /li /ulh3bNice to have /b /h3ulliScripting for automation and characterization (Python, Tcl). /liliExperience with memory compiler development, characterization, or verification. /liliDTCO or STCO experience aligning device, bitcell, and periphery choices with product goals. /liliA creative mindset and a drive for continuous improvement aimed at extreme hardware optimization. /li /ulh3Apply /h3pSend your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug how you solved it, an intro on what you like to do and how you see yourself as an engineer) /ph3Interview flow (indicative) /h3ulli30‑min intro with HR (role/context) /liliSecond Technical Deep Dive /lili(Optional) Third Technical Deep Dive /liliSystems/product conversation with management /li /ul /p #J-18808-Ljbffr
Senior Custom Design Engineer
