Senior Engineer – Backend (Physical Design & Timing)

ppLocation: Zürich, Switzerland Seniority: 5+ years (physical design with a timing focus) /ppOwn timing closure and sign-off for complex IP and SoC blocks that integrate our full-custom ComputeRAM® macros. You will drive Static Timing Analysis across corners and modes, shape clean constraints, partner closely with synthesis, place-and-route, and clock-tree teams, and lead ECO loops to convergence. Your work ensures robust clocks, predictable closure, and high-quality sign-off on modern nodes. You will work closely with our full-custom team to integrate our custom IPs into the traditional digital backend flow. /ph3bWhat you’ll do /b /h3ulliBuild, refine, and maintain timing constraints for blocks and top-level designs, including clocks, generated clocks, I/O timing, and exceptions. /liliRun STA across all relevant corners and modes, close setup and hold, and manage variation and correlation from synthesis to PR to sign-off. /liliGuide clock-tree strategy and debugging with clear targets for skew, jitter, and latency; collaborate with PR on placement, buffering, and routing choices that affect timing. /liliLead timing and functional ECOs, track impacts, and land repeatable closure with minimal overhead. /liliSupport gate-level verification needs with timing data, and ensure timing/constraints remain consistent with sign-off views. /liliAutomate timing checks, report generation, and regressions using scripting, and contribute checklists and documentation that others can reuse. /li /ulh3bOutcomes (first 18 months) /b /h3ulliClean timing closure at block and top level across all defined corners and modes, with stable constraints and traceable waivers. /liliDocumented timing methodology adopted by the team, with measurable reductions in ECO cycles and predictable time-to-close. /liliCorrelated results between synthesis, PR, and sign-off, demonstrated by repeatable reports and post-route margins on critical paths. /li /ulh3bRequirements /b /h3ulli5+ years in ASIC physical design with a strong emphasis on timing closure and sign-off. /liliFamiliarity with STA tools and flows, including clocking, cross-domain concerns, multi-clock designs, and hierarchical closure. /liliHands-on experience working with synthesis and place-and-route to drive timing-aware decisions and guide ECOs to closure. /liliScripting ability to automate timing analysis and reporting. /liliA collaborative approach with front-end, backend, and verification teams. /li /ulh3bNice to have /b /h3ulliExperience with power-aware and low-power backend. /liliBackground in scan and test timing, and awareness of verification and physical verification interactions with timing. /liliExposure to advanced nodes and hierarchical sign-off on large designs. /liliContext working on accelerators or memory-adjacent designs where timing and integration are tightly coupled. /li /ulh3Apply /h3pSend your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug how you solved it, an intro on what you like to do and how you see yourself as an engineer) /ph3Interview flow (indicative) /h3ulli30-min intro with HR (role/context) /liliSecond Technical Deep Dive /lili(Optional) Third Technical Deep Dive /liliSystems/product conversation with management /li /ul /p #J-18808-Ljbffr