Senior Verification Engineer — RISC-V CPU Cores

TechBiz Global GmbH is seeking a Senior Verification Engineer in Basel-Landschaft, Switzerland. In this role, you will be integral to the Verification Team, ensuring the functionality of digital designs for RISC-V CPU cores. The ideal candidate will have a Master's or PhD, with over 8 years of experience in the industry and proficiency in SystemVerilog, UVM, and various scripting languages. This is a fantastic opportunity for growth in an innovative environment. #J-18808-Ljbffr