Senior Analog & Mixed-Signal IC Design Engineer in Bern

Senior Analog & Mixed-Signal IC Design Engineer in Bern

Bern Vollzeit 63000 - 77000 € / Jahr (geschätzt) Vor Ort
Technify Talent

Auf einen Blick

  • Aufgaben: Leite die Entwicklung von ASIC-Architekturen und setze Kundenanforderungen in robuste Lösungen um.
  • Unternehmen: Innovatives Schweizer Halbleiterunternehmen mit Fokus auf kundenspezifische Lösungen.
  • Vorteile: Attraktives Gehalt, flexible Arbeitszeiten und Möglichkeiten zur beruflichen Weiterentwicklung.
  • Weitere Informationen: Tolle Karrierechancen in einem kreativen und kollaborativen Umfeld.
  • Warum dieser Job: Gestalte die Zukunft der Technologie mit fortschrittlichen Halbleiterlösungen und arbeite in einem dynamischen Team.
  • Qualifikationen: MSc oder PhD in Elektrotechnik und Erfahrung in analoger/mischsignal IC-Entwicklung.

Das prognostizierte Gehalt liegt zwischen 63000 - 77000 € pro Jahr.

Senior Analog & Mixed-Signal IC Design Engineer An exciting opportunity has arisen to join a specialist Swiss semiconductor business developing innovative, customer-specific ASIC solutions across analog, mixed-signal and low-power technologies.

The business is seeking a Senior Analog & Mixed-Signal IC Design Engineer to lead ASIC architecture and development, translating customer requirements into robust silicon solutions.

You will contribute across the full design lifecycle, from circuit design and simulation through to verification and silicon validation, working alongside multidisciplinary engineering teams on advanced semiconductor technologies.

What you’ll do as a Senior Analog & Mixed-Signal IC Design

Engineer: Define analog and mixed-signal ASIC architectures, translating customer requirements into detailed technical specifications.

Design and optimise low-power CMOS analog circuits and mixed-signal IP blocks, including amplifiers, voltage references, regulators, ADCs/DACs, oscillators and sensor interfaces.

Conduct feasibility studies, power-budget assessments and design trade-offs, balancing power, performance, area and cost.

Perform schematic design, simulation, verification and post-layout validation using industry-standard EDA tools.

Collaborate with digital, verification, layout and product engineering teams throughout the ASIC development lifecycle.

Support silicon bring-up, characterisation and customer design reviews, acting as a technical point of contact where required.

What you’ll bring as a Senior Analog & Mixed-Signal IC Design

Engineer: MSc or Ph D in Electronics Engineering, Microelectronics or a related discipline.

Technical lead level experience in analog and/or mixed-signal IC design, ideally within a semiconductor or ASIC development environment.

Strong expertise in CMOS analog design, including low‑power and low‑voltage circuit techniques.

Hands‑on experience with analog IP such as amplifiers, ADCs/DACs, voltage references, regulators and sensor interfaces.

Experience with ASIC architecture, circuit simulation, verification and silicon validation.

Proficiency with industry‑standard EDA tools, particularly Cadence Virtuoso, Spectre and/or Siemens EDA.

Strong understanding of analog fundamentals, noise optimisation, semiconductor processes and circuit reliability.

Exposure to industrial, automotive, medical or battery‑powered applications would be advantageous.

Strong communication skills and the ability to collaborate across multidisciplinary teams and engage directly with customers.

Senior Analog & Mixed-Signal IC Design Engineer in Bern Arbeitgeber: Technify Talent

Technify Talent bietet spannende Karrieremöglichkeiten in der Halbleiterindustrie und legt Wert auf Wachstum und Zusammenarbeit. Mitarbeiter profitieren von einem dynamischen Arbeitsumfeld, das Innovation und technische Exzellenz fördert.

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Kontaktdaten:

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Wir glauben, dass du diese Fähigkeiten brauchst, um Senior Analog & Mixed-Signal IC Design Engineer in Bern mit Bravour zu bestehen

Analog IC Design
Mixed-Signal IC Design
ASIC Architecture
Low-Power CMOS Design
Circuit Simulation
Verification
Silicon Validation