Senior FPGA Developer (SystemVerilog)

The Role

The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end ‑ to ‑ end RTL ownership on AMD/Xilinx (Artix ‑ 7, Kintex UltraScale): architect, implement, verify, and close timing on high ‑ rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer.

The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring ‑ up, and deliver reproducible, versioned bitstreams.

The Responsibilities

• RTL architecture, interfaces, and rather high‑speed datapaths
• Owning SystemVerilog RTL architecture/implementation for Artix ‑ 7 and Kintex UltraScale (SystemVerilog, Vivado)
• Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third ‑ party MAC/PCS IP
• Building deterministic acquisition/timing/sifting layers - packetization, buffering, alignment; robust clocking/CDC/reset; custom low ‑ level protocols - and bridging them to high ‑ throughput interfaces (DDR/PCIe)
• Defining clear AXI/AXI ‑ Stream boundaries and register maps for SW/FW integration
• Constraints, timing closure, and floorplanning
• Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners
• Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin
• Verification and CI
• Establishing a professional verification environment with ModelSim/Questa; developing self ‑ checking testbenches and regression suites; integrating Python/cocotb co ‑ simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as appropriate)
• Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW ‑ in ‑ the ‑ loop smoke tests
• Bring‑up, debug, and releases
• Board bring‑up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring‑up
• Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts
• Cross‑team collaboration and mentoring
• Driving system integration with SW/FW: register/driver contracts, throughput/latency budgets, HIL
• Mentoring a junior engineer; codifying style guides, reviews, and design documentation

The Requirements

• 5+ years production FPGA on AMD/Xilinx; expert SystemVerilog RTL
• Demonstrated mentoring of junior engineers
• Strong constraints/timing (XDC), CDC/reset, and practical floorplanning; consistent timing closure
• Hands ‑ on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third ‑ party MAC/PCS IP
• Strong verification background; experience with self-checking testbenches and regression testing, proficiency with ModelSim/Questa. Knowledge of OSVVM/UVM is a plus
• CI for HDL: scripted sim/synth/impl (Tcl/Make/Python), lint, artifact/version management; board bring ‑ up and ILA ‑ based debug
• System integration with SW/FW: register maps, driver contracts, HIL
• Proficiency in written and spoken English
• Ability to be on‑site in Munich or Potsdam offices to work with hardware, when required
• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship.
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have

• AXI4/AXI ‑ Stream expertise and DMA performance tuning
• Formal verification exposure
• Scripting for automation (Python/Tcl) and CI systems (GitHub Actions/Jenkins)
• MicroBlaze/Zynq ecosystems and low ‑ level FW/C driver collaboration
• Proven delivery on Artix ‑ 7 and/or Kintex UltraScale with Vivado

The Rewards

We are an international team of quantum technology experts and dedicated business creatives that are working to bring quantum-enabled solutions to the global market. Our brilliant team members enjoy a high degree of freedom working remotely or joining one of our office spaces. We have a vibrant, enthusiastic, passionate and creative culture driven by trust, excellence and continuous improvement. If you join the Terra Quantum team, you can expect: An opportunity to work with some of the brightest minds in the pioneering field of Quantum Technologies as well as an experienced and progressive Lea

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