IP Design Flow & Methodology Development Design, build, and support unified front-to-back design flows for mixed-signal IP development, bridging analog schematic/layout environments with digital implementation environments Define and enforce best practices for IP reuse, modularity, and multi-process node portability Mixed-Signal Verification & Modeling Establish robust Analog/Mixed-Signal (AMS) verification methodologies to enable automated, top-level co-simulations Standardize and automate the generation of high-quality behavioral models to enable early system-level simulations for IP consumers Interface Timing & Sign-Off Define methodologies for timing closure across analog-digital IP interfaces, including Static Timing Analysis (STA) on mixed-signal boundaries and constraint generation Build and automate physical verification sign-off flows (DRC/LVS/PEX, EM/IR drop, and reliability analysis) tailored for IP integration CAD Automation & Scripting 1. Develop and maintain robust automation scripts (Python, Tcl, SKILL, Perl) to minimize human error, automate repetitive design tasks, and accelerate regression testing IP Packaging & Release Management Define standard IP delivery packages (including Liberty files/lib, LEF/GDS, CDL, behavioral models, and integration guidelines) Manage design data, workspaces, and IP version control utilizing configuration management systems Qualifications Education: Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 10+ years of experience in CAD, design methodology, or IP development (analog, digital, or mixed-signal). Mixed‑Signal Flow Expertise: Strong hands‑on experience with industry‑standard EDA environments. Analog/Custom: Cadence Virtuoso (ADE, Spectre), Synopsys Custom Compiler. Digital Front/Back‑End: Synopsys Design Compiler/PrimeTime, Cadence Genus/Innovus. Mixed‑Signal Verification: Cadence Xcelium/AMS Designer, Synopsys VCS/XA. Scripting Skills: Proficiency in scripting languages used in modern EDA flows (Tcl, Python, SKILL, Shell scripting). IP‑Specific Knowledge: Deep understanding of IP packaging, process design kits (PDKs), physical extraction (PEX/EM/IR), and boundary timing constraints. #J-18808-Ljbffr
Standorte
IP Methodology & Design Flow Engineer in Großmehring, München Arbeitgeber: TSMC - Taiwan Semiconductor Manufacturing Company Limited
Als Arbeitgeber bieten wir dir die Möglichkeit, in einem dynamischen und internationalen Team zu arbeiten, das sich auf Spitzentechnologie spezialisiert hat. Mit einem einzigartigen Ausbildungsaufenthalt in Taiwan und der Chance, Arbeitsabläufe aktiv mitzugestalten, fördern wir deine persönliche und berufliche Entwicklung in einem Umfeld, das Sicherheit und Zusammenarbeit großschreibt. Bei uns erhältst du nicht nur Zugang zu modernsten Technologien, sondern auch die Möglichkeit, Teil einer neuen Mitarbeiterkultur zu werden, die auf Teamarbeit und Innovation basiert.
Kontaktdaten:
TSMC - Taiwan Semiconductor Manufacturing Company Limited Recruiting-Team
