Digital Design Lead

Taiwan Semiconductor Manufacturing Company Ltd. (“TSMC”) is the world’s leading semiconductor foundry. Headquartered in Taiwan, the Company has operation facilities worldwide and the largest logic chip manufacturing capacity in the global semiconductor industry. The Company employs a global workforce of over 82,000 and recorded revenue over US$90 billion in 2024. TSMC produces the chips that are found in smartphones, tablets, computers, smart TVs, cars, laptops, game consoles, data centers, and many more applications. TSMC sells to a wide variety of customers, including most leading semiconductor companies.

At the TSMC EU Design Center, you’ll work in an exceptional technology and design team to refine your technical and leadership skills within the world\’s most advanced design service ecosystem. You\’ll be contributing to the forefront of semiconductor technology, including cutting-edge nonvolatile memory solutions like MRAM and RRAM. Your main focus will be to assist our leading customers in delivering state-of-the-art products that have a transformative impact on people\’s lives.

Your work will enable chip innovation by developing and optimizing all aspects in the pre-silicon design flow, including:

1. Develop internal test chips as TSMC design-process co-optimization vehicles.
2. Develop MRAM/RRAM macros and compilers as the foundation IP of TSMC process.

Job Responsibilities:

1. Lead a team in the development of embedded nonvolatile memory test chips and intellectual property (IP). The primary responsibilities include:
2. Define, explore, and document the architecture and micro-architecture of RTL designs based on specified requirements.
3. Collaborate with circuit design and product engineering teams to clarify macro interfaces, as well as testing and manufacturing requirements.
4. Implement the defined architecture and micro-architecture using synthesizable Verilog or System Verilog, adhering to established coding guidelines.
5. Develop and document a comprehensive verification plan, implementing it through Verilog, System Verilog, and preferably UVM.
6. Demonstrate proficiency with at least one linting tool. Collaborate with the P&R team to specify SDC for synthesis and P&R, perform logic synthesis (using tools such as Design Compiler or Cadence), and conduct LEC (Logic Equivalency Checking) and STA analysis.
7. Identify design and design flow problems suitable for automation. Specify and document the input specifications and automation programs/utilities. Develop programs/scripts for automation using Python, C/C++, or other common scripting languages.
8. Conduct Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) checks and design. Collaborate with circuit teams, product engineering, and test engineering to debug and validate the test chip.

Job Qualifications:

1. Master\’s degree or above in Electrical Engineering or a related field.
2. Over 10 years of experience in logic design or circuit design for non-volatile memory technologies, including flash memory, RRAM, MRAM, or PCRAM.
3. More than 5 years of experience in a technical leadership role, demonstrating strong team leadership and problem-solving skills.
4. Proficient in using EDA tools and methodologies for both custom and digital design of non-volatile memory.

It is the policy of TSMC EU to provide equal employment opportunity (EEO) to all persons regardless of age, color, ethnic and national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status, or any other characteristic protected by applicable law.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Design and Engineering

Industries

Semiconductor Manufacturing

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