Role Overview
We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCsand Chipletstargeting AI, HPC, and Networking applications. This role requires deepexpertisein RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success.
What You’ll Do
Design and implement high-quality RTL for complex SoC components and subsystems
Own micro-architecture definition and execution for performance-critical blocks
Develop designs that scale across IP, subsystem, and full SoC integration
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Integrate andoptimizehigh-speed IO protocols such as:
- PCIe / CXL
- Ethernet (various speeds)
- UCIe (chiplet interconnects)
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Ensure robust design practices for:
- Timing closure
- Power efficiency
- Area optimization
Collaborate closely with architecture, DV, physical design, and firmware teams
Drive design quality initiatives including lint, CDC, RDC, and formal verification
Support emulation, prototyping, and silicon bring-up
Contribute to building reusable design components and IPs across multiple programs
Leverage automation and AI tools to improve RTL productivity and design quality
What We’re Looking For
Bachelor’s/Master’s degree in Electrical Engineeringor related field
8+ years of relevant experience in RTL design and micro-architecture
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Strongexpertisein:
- Verilog/SystemVerilog
- Digital design fundamentals
- High-performance and low-power design techniques
- Experience designing for large SoCs in AI, HPC, or Networking domains
Solid understanding of high-speed IO protocols :UCIe, PCIe, Ethernet
Experience with multi-clock, high-bandwidth, and latency-sensitive designs
Strong debugging and problem-solving skills
Good to Have
Experience with memory interfaces (DDR, HBM, LPDDR)
Familiarity with coherency protocols and interconnect fabrics
Exposure to synthesis, STA, and physical design constraints
Experience with emulation or FPGA prototyping
Working knowledge ofscripting (Python, Tcl)
Key Attributes
Strong ownership and attention to detail
Focus on quality and first-pass silicon success
Ability to work across teams in a fast-paced environment
Bias toward scalable, reusable, and clean design
Success in This Role Looks Like
High-quality RTL with minimal re-spins
Successful integration into complex SoCs
Performance, power, and area targets met
Contribution to reusable IP and design frameworks
Location
Hybrid / On-site – Bengaluru
