Are you an experienced ASIC Physical Design leader ready to take ownership of complex SoC implementation, drive PPA optimisation and lead high-performing engineering teams?We’re looking for a Senior ASIC Physical Design Lead with deep hands-on RTL-to-GDSII expertise, a strong track record of successful silicon tapeouts, and the technical leadership skills to deliver robust, power-efficient, high-performance semiconductor designs.This is an opportunity to shape physical design methodologies, solve challenging implementation problems and drive projects from synthesis through to final sign-off and tapeout.ResponsibilitiesLead RTL-to-GDSII implementation of complex ASICs and SoC subsystems, from synthesis through to sign-off and tapeout.Drive power, performance and area improvements, achieving predictable timing closure and high-quality implementation.Oversee and contribute hands-on to synthesis, floorplanning, placement and routing (P&R), clock tree synthesis (CTS), static timing analysis (STA), parasitic extraction and engineering change order (ECO) closure.Define and maintain scalable physical design methodologies, constraints, technology libraries, PDK integration and sign-off flows.Manage multi-corner multi-mode (MCMM) timing closure, setup/hold optimisation, power integrity, IR drop, electromigration (EM) and physical verification.Lead the integration of analog/mixed-signal blocks, SRAMs, hard macros and I/O within hierarchical digital-on-top ASIC architectures.Implement UPF/CPF-based methodologies, including multi-voltage domains, power gating, isolation, retention and level shifting.Define clocking strategies, manage hierarchical integration and address clock domain crossing (CDC) considerations.Work closely with DFT teams on scan insertion, MBIST integration, test timing and design-for-test requirements.Develop and optimise physical design automation using Tcl, Python, version control and CI/CD methodologies.Build, mentor and lead physical design engineers, setting technical standards, ownership models and delivery milestones.Partner with RTL, digital design, full-custom layout and foundry teams to resolve implementation challenges and deliver successful tapeouts.Experience requiredDegree in Electrical/Electronic Engineering, Microelectronics or a related discipline.10+ years of ASIC Physical Design experience and at least two successful tapeouts.Strong expertise in Synopsys/Cadence tools, STA, P&R, CTS, ECOs and power integrity.Experience with hierarchical design, UPF/CPF, PPA optimisation and design automation.Proven technical leadership and cross-functional collaboration skills.Excellent analytical, problem-solving, communication and cross-functional collaboration skills.This role is ideal for a senior physical design engineer who combines deep technical expertise with the ability to influence implementation strategy, develop engineering talent and deliver complex silicon projects. #J-18808-Ljbffr
Technical Lead – Physical Design (RTL to GDSII) in Zürich Arbeitgeber: Beagle
Unser Unternehmen ist ein hervorragender Arbeitgeber, der innovative Technologien in einem dynamischen Umfeld fördert. In Hannover bieten wir nicht nur wettbewerbsfähige Gehälter und flexible Arbeitszeiten, sondern auch eine unterstützende Unternehmenskultur, die auf Zusammenarbeit und kontinuierlichem Lernen basiert. Unsere Mitarbeiter haben die Möglichkeit, an spannenden Projekten zu arbeiten, ihre Fähigkeiten weiterzuentwickeln und aktiv zur Gestaltung der nächsten Generation von Produkten beizutragen.
