Cambridge, UK | Full-time | Permanent | Hybrid
Salary: £60,000to £88,000(DOE) + Bonus + Benefits
The salary range for this role is broad, as we are able to consider varying levels of experience.Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements.
Wewillalsoconsider part-timeapplicationsforthis role. Pleaseindicateyour preferred working schedulein yourcoverletter.
About us
Riverlane’smission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved.Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills,talentand passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
We have an exceptional opportunity for a Verification / Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems.
In thisexcitingroleyou'llhave end-to-end visibility across the entire stack,owningevery aspect of verification andshaping how quality and reliability are built into ourcutting-edgetechnology.You do not need a background in quantum computing! You will learn this along the way.
What you will do
- Proactively work with designers and architects to define verification plans based on design specifications. You willtakefull ownership of detailed test strategies across block-level and system-level designs.
- Develop and implement scalable testbenches, including checkers, referencemodelsand coverage groups inSystemVerilog. You will implement self-testing, directed and random teststo ensure every part of the system performsflawlessly.
- Maintain thehealth and evolution of thedesign verificationenvironment, trackingof regressions, coveragemetricsand bugsto ensure our systems meet the highest standards of quality and reliability.
What we need
- Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
- Proven experience of testbench design with verification frameworks like UVM/OVM.
- Knowledge of SystemVerilog assertion (SVA).
- Exposure to different programming languages, such as C,C++and Python.
- A proactive person who can independently define the scope of work.
- A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback.
- Ability toworkeffectivelywith ambiguity and changing requirements.
- Experience debugging across RTL, simulation, and hardware
Even better if…
- Formal verification experience.
What can you expect from us
- A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme
- Equity, so that our team can share in the long-term success of Riverlane
- 28 days annual leave,plus bank holidays and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory,physicsand maths) and over 20 different nationalities
- A learning environment that encourages individual, team and company growth anddevelopment, including a regular programme of learning events and training and conference budgets
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
Women and other underrepresented groups may be less likely to apply for a role unless they meet all ornearly allof the requirements.If this applies to you, we still encourage you to apply - you may be a great fit, even if youdon’tmeet every single qualification.We’dlove to hear from you.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.
GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see the privacy notice for further details.
If you have any queries, please contact com.
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Verification / Senior Verification Engineer Arbeitgeber: Riverlane
Riverlane ist ein hervorragender Arbeitgeber, der eine dynamische und inklusive Arbeitsumgebung in Cambridge, UK, bietet. Mit einem umfassenden Leistungspaket, das unter anderem private Krankenversicherung, Lebensversicherung und ein beitragsorientiertes Rentensystem umfasst, fördert das Unternehmen das individuelle und kollektive Wachstum seiner Mitarbeiter. Die Möglichkeit, an der Spitze der Quantenfehlerkorrektur zu arbeiten und sich in einem vielfältigen Team von Experten weiterzuentwickeln, macht Riverlane zu einem attraktiven Arbeitsplatz für alle, die bedeutungsvolle und lohnende Karrieren anstreben.
